<Flea86>
Never really took it too far beyond basic FM reception.. could use better noise filtering
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
<Flea86>
keesj: There's a similar Xilinx project that precedes it, but I could only find block diagrams of it and no source :(
<Flea86>
so I scraped together my own
<Flea86>
(well Ok, I borrowed the HDL based PLL decoder and that part isn't mine but does all the magic)
Xark has quit [Ping timeout: 246 seconds]
Xark has joined ##openfpga
<azonenberg>
keesj: nice
<azonenberg>
i love when people abuse FPGAs to do mixed signal stuff with a handful of passives
<azonenberg>
like my TRAGICLASER project doing 100base-TX ethernet, including differential transmit *with pre-emphasis*
<azonenberg>
using a couple of spartan6 IOBs and about a dozen resistors
Asu has joined ##openfpga
Flea86 has quit [Quit: Goodbye and thanks for all the dirty sand ;-)]
<sxpert>
when I need 2 modules to share constants (say they send commands to each other), do I need to specify the same list of things in both modules ?
<tnt>
sxpert: you can `define or localparam then and use `include for instance.
<sxpert>
ah, localparam are shared between modules when `include . ok.
<tnt>
well include is literally a cut and paste ...
<sxpert>
I miss-guessed those were local to the module
<tnt>
well they are, but if you include the file where you define them ...
<tnt>
(so you have a myconst.v file that you include in both your modules)
<s_frit>
azonenberg: is there any documentation on your pre-emphasis scheme? i'm looking for ways to hack improved tx performance on an up5k design i'm working on
<tnt>
Doh, I had completely forgotten than to be useful for larger bitwidth math an addcy/subcy instruction need also to AND the new Z flag with the prefious one ...
<sorear>
what common arches do that?
<sorear>
looks like m68k behaves as you describe, x86 doesn't
<tnt>
tbh, I didn't check . I know the recent picoblaze do (but older ones didn't) and it's just right now when trying to implement a 32b compare as 2 16 bit ones, that I realized that if you don't have this, it's annoying to get all the flags set ...
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined ##openfpga
<ZipCPU>
sxpert: Be aware with include files .... if you include something in one source file, you may or may not have those results in another depending on synthesis order
<ZipCPU>
The official Verilog synthesis model is that synthesis is to be accomplished as though all files were concatenated together first
rohitksingh_work has quit [Read error: Connection reset by peer]
<somlo>
zem: love the ULX3S, but would like a version with (a lot) more (S)DRAM -- is there a reasonable way to e.g., just include an SODIMM slot?
<q3k>
that reminds me we need to add ECP5 DDR DRAM support to litedram...
OmniMancer has quit [Quit: Leaving.]
<cr1901_modern>
is hyperdram supported?
<TD-Linux>
q3k, somehow the existence of litedram escaped me. I'm going to use this :)
rohitksingh has joined ##openfpga
<somlo>
yeah, studying litedram carefully is very near the top of my agenda over the next few weeks :)
<q3k>
somlo: if you have time and an ECP5 board with DDR DRAM, you could definitely try working on writing a PHY layer for that
<q3k>
somlo: TN1265 is my kryptonite
<q3k>
somlo: especially figure 31
* cr1901_modern
wants to make a hyperdram core. For "fun". For some metric of fun.
<cr1901_modern>
Seems a bit less screwy latency-wise than DDR/SDRAM (so I could say, create a litescope that can go beyond BRAM resources)
<TD-Linux>
I thought hyperdram actually had more latency
<cr1901_modern>
more consistent latency*. I.e. I can live w/ more latency if it means that an xfer from LA sample to memory is less likely to fail b/c "the memory backing isn't ready"
<TD-Linux>
just have a small queue
<tnt>
it's hyperram not hyperdram :p I think the whole point is that it hides the 'd' nature of it.
<TD-Linux>
I thought the main point was the lowered pin count
<tnt>
yeah, that too
<q3k>
i would like an ecp5 design with a SO-DIMM slot though
<tnt>
why ? so-dimm is so annying from a SI PoV.
<TD-Linux>
I was actually going to do one
<tnt>
(I mean vs just soldering the chips)
<TD-Linux>
but yeah I also came to the conclusion that soldering the chips was better
<q3k>
tnt: because it's cool
<q3k>
tnt: isn't that a valid reason? :P
<cr1901_modern>
I want to put a SIMM socket on my next FPGA board. 30 pin variant
<TD-Linux>
the sockets for sdram simms/dimms are hard to get
genii has joined ##openfpga
<gruetzkopf>
for old memory, yes
Asu has quit [Remote host closed the connection]
sgstair has quit [Read error: Connection reset by peer]
sgstair has joined ##openfpga
rohitksingh has quit [Ping timeout: 272 seconds]
Miyu has joined ##openfpga
rohitksingh has joined ##openfpga
jevinskie has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
dj_pi has joined ##openfpga
Asu has joined ##openfpga
dj_pi has quit [Ping timeout: 246 seconds]
<azonenberg>
s_frit: this requires a bit of hackery and wont work at speeds close to fmax of the I/O cell
<azonenberg>
s_frit: basically, I'm driving the Ethernet diffpairs using two FPGA push-pull outputs in an H-bridge configuration
<azonenberg>
with two equal valued resistors to reduce the voltage across the 100-ohm line from 3.3 to 1.0V
<azonenberg>
I need a second driver with a smaller resistor to do the same thing with 2.5V across the line, in order to do 10base-T or autonegotiation
<azonenberg>
In order to get cleaner transitions between the 100base-TX differential states (125 Mbps symbol rate so 8 ns per symbol) I run an OSERDES at 4x the symbol rate (500 Mbps)
<azonenberg>
and drive the 2.5V driver for 2ns at the start of certain symbols to provide extra drive current
<azonenberg>
Then tri-state it for the remaining 6ns of the UI
massi_ has joined ##openfpga
gsi__ is now known as gsi_
rohitksingh has quit [Ping timeout: 268 seconds]
m_w has joined ##openfpga
Laksen has joined ##openfpga
wolfspraul has quit [Quit: leaving]
wolfspraul has joined ##openfpga
wolfspraul has quit [Client Quit]
wolfspraul has joined ##openfpga
rohitksingh has joined ##openfpga
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
rohitksingh has quit [Remote host closed the connection]
azonenberg_work has quit [Quit: Leaving.]
azonenberg_work has joined ##openfpga
azonenberg_work has quit [Client Quit]
azonenberg_work has joined ##openfpga
Laksen has quit [Quit: Leaving]
massi_ has quit [Remote host closed the connection]
m_w has quit [Ping timeout: 240 seconds]
ayjay_t has quit [Read error: Connection reset by peer]
ayjay_t has joined ##openfpga
m_w has joined ##openfpga
genii has quit [Remote host closed the connection]