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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbOX
<_whitenotifier-9> [whitequark/Glasgow] whitequark 8b36261 - access.direct.demultiplexer: reset FIFOs when synchronizing.
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<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497632727?utm_source=github_status&utm_medium=notification
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<mithro> Anyone tried
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<shapr> mithro: that's neat, but vivado?
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<azonenberg> Holy moley, you can buy a 150 H inductor
<azonenberg> I... don't want to know how many turns are in that thing
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<Ultrasauce> the core is actually a black hole
<azonenberg> lol
<azonenberg> also FREESAMPLE is up to 331 components now and i still have to do six more rails in the PSU
<azonenberg> (possibly more if i add intermediate rails for LDOs)
<azonenberg> i can't imagine how crazy this board would be if i also had the FPGA and ethernet on it
<azonenberg> rather than using an INTEGRALSTICK
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<sxpert> azonenberg: what kind of a board is that ?
<azonenberg> sxpert: 10 GHz / 1 Tsps sampling oscilloscope
<azonenberg> with nice fun features like CDR trigger
<sorear> what's the fastest and/or tightest jitter limit signal between the FPGA board and the rest?
<azonenberg> sorear: um, probably 250 MHz with totally irrelevant jitter
<azonenberg> LD
<azonenberg> :D *
<azonenberg> the architecture was very carefully designed to keep the fpga clock tree out of any critical timing paths
<azonenberg> https://www.antikernel.net/temp/freesample.pdf is the WIP schematic
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* sxpert discovers wierd ass chips that he never heard of
<tnt> azonenberg: why the TLK10232 if you're not using the secnd channel ? Isn't the TLK10031 the same but with only 1 channel ?
<azonenberg> tnt: Because i have about 15 TLK10232 samples sitting around my lab waiting to get used :p
<sorear> I did not realize you were misusing a 10G PHY in quite this way
<azonenberg> i'd likely respin if this went into production
<azonenberg> sorear: lol
<azonenberg> Can you think of a better way to recover a clock off a high-speed serial signal? nobody sells CDR PLLs as a discrete component
<azonenberg> at least not past a few hundred Mbps
<azonenberg> so you basically have to use a full serdes IP and discard the data
<azonenberg> and fpga serdes are out b/c too much jitter on the clock tree etc
<tnt> azonenberg: otoh, after checking pricing it's really not that much cheaper.
<azonenberg> tnt: yeah power is the bigger issue
<azonenberg> power numbers for the tlk10232 with various blocks disabled are hard to find so i have to overdesign the psu to handle the whole thing
<azonenberg> Good news is, i can build an external CDR circuit on a different board and feed it into the external-clock input for testing
<sorear> so I read "fun features like CDR trigger" to imply data-dependent triggering, possibly with a shift register + comparator
<azonenberg> without a huge impact on performance
<azonenberg> sorear: For the moment the triggering is only clock recovery, there's no data dependence
<azonenberg> Pattern trigger at multiple Gbps is nontrivial
<azonenberg> but might be a wishlist feature for way further out
<azonenberg> the big thing is, the latency through the tlk10232 is unpredictable so i can't use it as a trigger source
<azonenberg> i'd have to build my own trigger circuit that ran at full line rate
<azonenberg> I could do it, using a shift register + comparator, however you'd be looking at $15ish per bit of the shreg plus $12ish for each comparator, plus passives and PCB area
<azonenberg> more importantly, as soon as your trigger is no longer free-running you can't lock a PLL to it, and your sample rate drops from 1 Tsps to 90 Gsps with much higher jitter
* sxpert knew he was in wierdo-land when he read SiGe on one of the datasheets ;-)
<azonenberg> Lol
<azonenberg> This board has $160 of comparators on it
<sxpert> yeah, saw that
<azonenberg> And $58 of discrete DFFs
<sxpert> had a few links to mouser on the search ;)
<azonenberg> The 74xx equivalents for 10G data have double digit price tags :p
<sxpert> 12 EUR flipflops
<azonenberg> Yep
<sxpert> I wonder what those trans-ocean cable termination systems are made of
<azonenberg> SiGe? :p
<sxpert> well the linerate is like 1+ Tbit/s
<azonenberg> yeah but that's after WDM
<azonenberg> its not one wavelength carrying that much
<sxpert> ah yeah
<azonenberg> it's DWDM and probably PAM4 on each wavelength (actually idk, PAM4 seems to be just hitting mainstream now)
<sxpert> it's like 100G "coherent" whatever that means
<sxpert> probably 404x25Gbit/s
<sxpert> argh
<sxpert> 40*4*25Gbit/s
<sxpert> then you need freaking lazers to shoot that across the ocean
<sxpert> hah, kintex ultrascale+ has "integrated 100G Ethernet MAC with RS-FEC and 150G Interlaken cores"
<sxpert> that will do it
<davidc__> heh, I saw a pricetag for a small multi 100Gbit WDM system. I'm fairly sure they are made of unobtainium
<sxpert> heh
<sorear> world market for maybe 6 multi 100Gbit WDM systems
<sorear> (yes, I know that's massively out of context, but the out of context quote has its own history now)
<davidc__> actually, the market is much much larger than that
<davidc__> anyone that operates a backbone uses them
<sxpert> sorear: either that, or vibranium from wakanga
<sxpert> sorear: yeah lol...
<sxpert> sorear: then there is the similar "nobody needs more that 10Gbit/s"
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<sxpert> ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
<sxpert> what should I do ?
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<daveshah> sxpert: absolutely nothing, it's an artefact of how Yosys interacts with ABC
<sxpert> ah ok
* sxpert is cutting up his bigger modules into smaller ones
<sxpert> trying to make that all more readable
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+1/-0/±2] https://git.io/fhbWG
<_whitenotifier-9> [whitequark/Glasgow] whitequark b9de91e - applet.yamaha_opl: add a web interface.
<_whitenotifier-9> [Glasgow] Failure. The Travis CI build failed - https://travis-ci.org/whitequark/Glasgow/builds/497750127?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbWc
<_whitenotifier-9> [whitequark/Glasgow] whitequark a7f569f - software: aiohttp is now a global dependency.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497750687?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhblb
<_whitenotifier-9> [whitequark/Glasgow] whitequark e69e2c9 - appplet.yamaha_opl: web: create buffers and sources via context.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497773989?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fhb0J
<_whitenotifier-9> [whitequark/Glasgow] whitequark 972283b - applet.yamaha_opl: support looped VGMs.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497848420?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fhb0P
<_whitenotifier-9> [whitequark/Glasgow] whitequark e67787c - applet.yamaha_opl: make looping almost completely seamless.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497856770?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fhbEh
<_whitenotifier-9> [whitequark/Glasgow] whitequark 773ed0d - applet.yamaha_opl: improve reset sequence to be completely robust.
<_whitenotifier-9> [whitequark/Glasgow] whitequark ac940e5 - applet.yamaha_opl: sanity check features used by OPL client.
<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbuv
<_whitenotifier-9> [whitequark/Glasgow] whitequark d6127b9 - applet.yamaha_opl: sanity check features used by OPL client.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497875098?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497875726?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbuT
<_whitenotifier-9> [whitequark/Glasgow] whitequark 164407f - applet.yamaha_opl: restructured documentation. NFC.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497876709?utm_source=github_status&utm_medium=notification
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fhbug
<_whitenotifier-9> [whitequark/Glasgow] whitequark 9a92810 - applet.yamaha_opl: reset feature level with registers.
<_whitenotifier-9> [whitequark/Glasgow] whitequark 72fb637 - applet.yamaha_opl: web: fix a glitch at the end of playback.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497881723?utm_source=github_status&utm_medium=notification
<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbuF
<_whitenotifier-9> [whitequark/Glasgow] whitequark 7d9ce09 - applet.yamaha_opl: detect dual/special OPL2 in VGM.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497886586?utm_source=github_status&utm_medium=notification
<shapr> is glasgow purchasable?
* shapr subscribes
<whitequark> nod
<TD-Linux> shapr, I may have one I can send you. keep in mind the revb limitations tho
<TD-Linux> oh I see it's been bolded and starred in the readme
<shapr> I'm a n00b, who does not understand
<shapr> TD-Linux: but I appreciate the thought :-)
<shapr> I'll wait until there's a noob friendly rev for sale
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhbgP
<_whitenotifier-9> [whitequark/Glasgow] whitequark cb3c9d2 - applet.yamaha_opl: accumulate fractional sample delays.
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<_whitenotifier-9> [whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fhb2B
<_whitenotifier-9> [whitequark/Glasgow] whitequark 74ae318 - protocol.vgm: fix parsing of variable length header.
<_whitenotifier-9> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/whitequark/Glasgow/builds/497922060?utm_source=github_status&utm_medium=notification