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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 3fc0809 - applet.jtag: separate IR/IDCODE scan from segmentation.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 13d9864 - applet.yamaha_opl: simplify. NFC.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark a39390b - applet.yamaha_opl: document choice of MCLK frequency. NFC.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 2c5d360 - protocol.vgm: add missing VGMStreamPlayer stub.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 952b16b - applet.jtag_pinout: never try to detect TRST# with 4 only pins.
20:25
<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark c87e280 - applet.jtag_pinout: fix type confusion between bit and pin numbers.
20:25
<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark c2a4bed - applet.jtag_pinout: fix failure to detect TRST# on pin 0.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 11fd032 - applet.jtag_pinout: improve messages related to detection of TRST#.
21:24
<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark e2d1303 - applet.jtag: fix misdetection of 32-bit DRs at end of chain as truncated.
21:24
<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark e1fb23d - applet.jtag: enumerate-ir: fix endianness.
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<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark da71e22 - applet.jtag: pulse TRST# and reset TAPs when run.
21:37
<
_whitenotifier-9 >
[whitequark/Glasgow] whitequark 46f6594 - arch.mips.ejtag: fix definition of DR_IMPCODE.
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<
AndresNavarro >
I am starting to get some decent results for the XO2 family
23:46
<
AndresNavarro >
Thanks to the work by cr1901_modern
23:48
<
AndresNavarro >
I am still not 100% sure these are correct but they are starting to look good
23:48
<
AndresNavarro >
I am now figuring out the best way to incorporate the changes to libtrellis without polluting the codebase too much
23:50
<
AndresNavarro >
I think we can do this without the need to spin out a new project, the differences are for now pretty minimal (1-based columns instead of 0-based, inverse order or rows for the frames, different order of commands in the bitstream, some weird tile names, etc)
23:54
<
azonenberg_work >
The less toolchains we have the better
23:54
<
azonenberg_work >
ideally i'd like one for 2D fabric FPGAs and one for crossbar CPLDs
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23:55
<
azonenberg_work >
and then just add support for IP blocks and architecture-specific stuff as needed
23:56
<
AndresNavarro >
that would be ideal
23:56
<
AndresNavarro >
Maybe as we get to understand these better we may get there
23:56
<
azonenberg_work >
That was one of the reasons i was so strongly against rqou making his own toolchain for coolrunner in rust
23:56
<
azonenberg_work >
rather than building on, or totally redoing, my existing C++ greenpak tools
23:57
<
azonenberg_work >
i dont want a situation where we have 30 competing toolchains that each support one architecture and have incompatible constraint formats and CLI syntaxes et
23:57
<
azonenberg_work >
and where improvements in techmapping and optimization for one can't be easily ported to another
23:57
<
azonenberg_work >
i'd rather keep it nice and modular like yosys and simply have some passes not used in some architectures
23:58
<
azonenberg_work >
nextpnr seems like a nice basleine
23:58
<
AndresNavarro >
If I was doing it from scratch I probably wouldn't do it in C++ and python, but it would have been silly to start over when so much work was done
23:58
<
AndresNavarro >
Yeah, I still haven't had a look, but from the presentation I watched it seems quite nice
23:59
<
azonenberg_work >
i mean ideally i want to unify prjxray and prjtrellis... separate tools for bitstream RE are fine (to some extent)
23:59
<
azonenberg_work >
synthesis is pretty unified now in yosys
23:59
<
azonenberg_work >
so if we can get par and bitstream generation sharing as much code as possible that would be ideal
23:59
<
AndresNavarro >
I'll have to work on nextpnr when I get a little more of this figured out