15:32 <somlo> Does anyone know of an example of using litedram to just spit out Verilog for the memory controller itself (axi on one side, dram chip pins on the other)?

15:32 <somlo> E.g., for the nexys4ddr, as a starting point?

15:32 <somlo> The included demos look like they want to build a whole SoC in one giant Verilog blob, and I'm in that weird intermediate stage on the learning curve where figuring out how to fine-tune what's getting generated could be sped up orders of magnitude if only I had an example... :)

18:27 <RaYmAn> daveshah: damn, you're fast! :P

18:27 <daveshah> :)

21:36 <_florent_> somlo: this is what you want: https://github.com/enjoy-digital/litedram/blob/master/examples/litedram_gen.py

21:36 <_florent_> somlo: i have a nex4ddr and can add a config for it