19:22 <daveshah> _florent_: ping?

19:47 <_florent_> daveshah: hi

19:47 <daveshah> I saw you've been playing a bit with the ECP5 DRAM stuff

19:48 <daveshah> coincidentally I've been looking at the nextpnr side these last few days

19:48 <daveshah> I'm still not exactly sure of the DQSBUFM behaviour, but my poking thus far seems to indicate you have to assert READ0/READ1 to get reads working at all

19:48 <_florent_> yes i'm looking at it a little bit

19:49 <_florent_> i just prepared things, haven't tested on hardware yet

19:49 <q3k> awesome

19:49 <q3k> it's been scaring me away for quite a while

19:49 <q3k> _florent_: you have a versa-ecp5, right?

19:50 <_florent_> daveshah: i just added some probe in the design to look at that, i'm also wondering if we have to assert READ0/READ1 or not

19:50 <_florent_> q3k: yes it's on the versa-ecp5

19:50 <daveshah> I've just created this harness for probing the DQSBUFM sim model

19:50 <daveshah> https://gist.github.com/daveshah1/ba7fc993c7705a91396f7708b4bb018b

19:50 <daveshah> it doesn't do anything much yet

19:51 <_florent_> daveshah: ok i'll look at that

19:52 <_florent_> daveshah: i'll do some first tests tomorrow on hardware

19:52 <daveshah> awesome

19:52 <_florent_> i'll also look at the sim model

19:53 <_florent_> i would like to just use the DQSBUFM to provide the dqs clocks, rdpntr, wrpntr but as you say, not sure it will work like that

19:56 <sorear> what's the sim model story for this stuff likely to be?

19:57 <daveshah> sorear: not a priority

19:58 <daveshah> but the lattice models are abysmal so I'd like to see replacements at some point

20:37 <somlo> _florent_, daveshah: I'm at a stage in my project where I could use (verilog sources for) a DRAM controller for my ecp5 (5g) versa; I have the board, and a working rocket-chip compiled with yosys/nextpnr that's ready to start accessing the DRAM :) So I was wondering if/how I can help: I am fluent in Verilog, and have a rudimentary understanding of Chisel -- is it time to learn Migen before I can be useful here? :)

20:41 <whitequark> it's always time to learn migen :P

20:42 <shapr> clash-lang! learning Haskell is something you can do over the weekend

20:43 <shapr> ok, maybe not

20:47 <somlo> it figures that all my necessary building blocks are written in different verilog-generating meta-languages, so I get to be a n00b at all of them instead of just one :D

21:19 <_florent_> somlo: once we have a first version of the controller, testing it with a different cpu (rocket-chip) or different configuration and giving feedback will help

21:21 <sorear> but daveshah is using rocket-chip, so rocket-chip wouldn't be a different cpu?

21:22 <whitequark> there's a risc-v implementation in nmigen

21:22 <whitequark> called minerva

21:22 <daveshah> sorear: it's somlo who is using rocket-chip

21:22 <daveshah> Different cpu was wrt the litex defaults

21:24 <daveshah> whitequark: oh interesting, I'll look into that

21:24 <whitequark> https://github.com/lambdaconcept/minerva

22:04 <somlo> ok, so in the interim, migen tutorial, here I come :)

22:12 <catplant> somlo: are you writing one, or following one?

22:34 <daveshah> _florent_: playing with the sim model, I think tieing both READ0 and READ1 to 1'b1 will do what you want

22:48 <_florent_> daveshah: thanks, yes that's what i also found playing with your sim: https://github.com/enjoy-digital/versa_ecp5_dram/commit/9dd77b7bad9ef903347fbcb508c704167390e4cf :)

22:53 <daveshah> _florent_: also while playing about with the pnr tests on hardware, I found that DQSBUFM would sometimes misbehave if it isn't reset at startup

22:53 <daveshah> I think it needs to be reset once clocks are stable

22:57 <_florent_> daveshah: ok thanks, i just added it