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<TD-Linux> why don't FPGA IOBs offer a synchronizer? it seems like it'd be a common use case
<TD-Linux> oh apparently 7 series does have this
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<omnitechnomancer> Do some of the DDR modes count?
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<Lofty> TD-Linux: one thing that comes to mind is that distributing the synchroniser allows for pretty lax internal timings
<Lofty> If it needs to get from pin A to gate B and B is on the other side of the chip, you can spread the routing delay across the flops
<omnitechnomancer> Makes one wonder why it would have placed gate B on the other side of the chip though
<Lofty> Because when you have all these flops, they could be closer to other more critical inputs
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<TD-Linux> I think you normally want synchronizer flops to be as close together as possible
<TD-Linux> but yeah also I suppose there isn't a huge benefit vs just normal flip flops
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<mithro> Love to hear peoples ideas around https://twitter.com/mithro/status/1292189637566320640 -- the more different ways people can come up with the better
<mithro> daveshah: I know that Dirk was looking into things like this
<daveshah> Yes, I think he made a DAC out of routing transistor short circuits
<daveshah> That was for measurement from outside the FPGA
<daveshah> But similar tricks might apply inside, too
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