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<
hell__ >
silly question: is there something like `Turing completeness` but for HDLs?
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<
Lofty >
hell__: that's actually a pretty good question, but I think a lot of HDLs are Turing complete because the underlying target is Turing complete
15:23
<
daveshah >
In particular, if you have unlimited access to NAND or NOR gates and either logic loop support or a dedicated storage element, then theoretically anything can be built
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<
hell__ >
just having NAND, NOR and some sort of storage would suffice
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<
hell__ >
thank you!
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<
vup >
(one of NAND or NOR is enough)
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<
hell__ >
(I forget)
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<
implr >
which relate the depth (and in turn size) of a circuit with a complexity class
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<
Lofty >
How dumb is it to consider using a USB port to power your theoretical FPGA board?
20:29
<
hell__ >
hrm, Glasgow isn't theoretical and is powered from a USB port
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<
Lofty >
e.g. the ECP5 Versa and DE10-Nano both come with their own power supplies and I'm more than a little tired of trying to find them
20:30
<
zyp >
completely depends on how much power you're gonna need
20:30
<
daveshah >
I deliberately designed the TrellisBoard to support USB power for this reason
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<
hell__ >
e.g. I don't think powering one of those FPGA devboards with SO-DIMM slots through USB is a good idea
20:30
<
daveshah >
Yes, with some bitstreams it technically breaks USB specs but hey ho
20:30
<
Lofty >
My target chip is a Cyclone 10 GX. It's difficult to estimate exactly how much power it's going to draw
20:31
<
daveshah >
The best option is to support both USB power and external DC in
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<
zyp >
hell__, I'm designing a board with a so-dimm slot that can be usb-powered :)
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<
daveshah >
Even if it is just a jumper like some of the Digilent boards
20:31
<
hell__ >
maybe even have some jumper to choose where to power the board from
20:31
<
zyp >
but I'm gonna support USB PD
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<
Lofty >
My target chip is a Cyclone 10 GX. It's difficult to estimate exactly how much power it's going to draw
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<
Lofty >
Thanks arrow keys
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<
Lofty >
Speaking of power supplies, it would appear my Versa power supply has gone missing
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<
Lofty >
Which is always a fantastic start
20:36
<
hell__ >
intel says there's th Excel-based Early Power Estimator
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<
hell__ >
32.5 MiB excel
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<
Lofty >
Predictably, it does not run under libreoffice
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<
hell__ >
you also tried it? :-)
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<
Lofty >
God, this is entirely unusable
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<
Lofty >
And I don't have Excel or anything to try this with
20:54
<
Lofty >
The only useful figure I got was that the FPGA statically draws 0.712W :P
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<
tpw_rules >
how did they get openssl into an xlsx
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<
tpw_rules >
xls, no less!
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