* hell__
runs into lots of shiny interesting-yet-not-useful things all the time
<scientes>
yeah, but FPGA similation is something that is so incredibly unpracticle that I it doesn't make sense to do wierd hacks with it
<tnt>
I haven't watched the talk but if I can run my fpga simulation faster on my gpu than my cpu, then why not ?
<scientes>
for the same reason that you shouldn't design an ASIC to parse your UTF-8
<scientes>
its like arguing which blind person is better at painting
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<tnt>
So ... you point is simulation is useless all together ?
<scientes>
no it can be useful, but it needs to be resiliant
<scientes>
like this probably wasn't even compiled with an open source tool chain
<tnt>
Ok, I'm lost and I don't have 43 min to watch that video. But " FPGA simulated on a GPU", just that description sounds super useful to me. If I can get the same output of some iverilog-gpu or gpurtl than I can from iverilog or cxxrtl but faster, that's something I'd want. Just like there are GPU accelerated SPICE simulator for large simulations ...
<daveshah>
One interesting use case I heard mentioned for GPU simulations was to run multiple vectors through the same design in parallel
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<ktemkin>
VLIW processing seems like a reasonably natural fit for logic simulation
<daveshah>
I think some of the Synopsys (or perhaps one of the others) ASIC emulation stuff actually has some custom silicon similar to a GPU but bitwise/integer optimised
<daveshah>
Cadence I think actually
<daveshah>
meanwhile, I've been looking into some GPU FPGA routing stuff recently
<daveshah>
not sure if anything will come if it though
<mangelis>
well if fpga sim on GPU can be faster than on CPU, then why not use it?
<mangelis>
for example i'm implementing a polygon rasterizer on the ecp5. verilator runs it perfectly but it's so slow that it's not possible to develop an application for the rasterizer hw that would run 50Hz in simulation
<mangelis>
scientes: afaik the creator of the challenge used yosys for synthesis and had some custom pnr tool
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<scientes>
mangelis, I am talking about the simulator, not the FPGA synthesis
<scientes>
oh, I see, "custom pnr tool"
<scientes>
but I am talking about the C compiler he used
<scientes>
I have not done GPU programming but understanding is that the nvidia extension to C are propritary
<scientes>
(and this is enabled by LLVM becoming a platform for non-free compilers)
<scientes>
instead of a compiler
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<Degi>
The SERDES problems seem to appear on diamond too, but now trellis seems to work for ktemkin?. (And trellis is 5-10x faster than diamond lol)
<OmniMancer>
scientes: It depends I believe there is at least a public PTX backend
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<scientes>
is the SERDES supported now?
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<ktemkin>
Degi: I wouldn't say it's working
<keesj>
I can't find an example of setting the output voltage of a bank on the ice40 is there not such a thing?
<tnt>
keesj: no
<tnt>
voltage is whatever you feed to vcc_io of that bank ...
<keesj>
ok.. I was kinda expecting this but still.. kind expected to find examples (also for differental pairs or similar)
<tnt>
differential pair has a special SB_IO setting.