jeanthom has quit [Ping timeout: 258 seconds]
mumptai has quit [Quit: Verlassend]
kristianpaul has quit [Read error: Connection reset by peer]
jaseg has quit [Ping timeout: 240 seconds]
jaseg has joined ##openfpga
kristianpaul has joined ##openfpga
peepsalot has joined ##openfpga
peeps[zen] has quit [Ping timeout: 258 seconds]
jaseg has quit [Ping timeout: 240 seconds]
jaseg has joined ##openfpga
Bike has quit [Quit: Lost terminal]
Degi has quit [Ping timeout: 240 seconds]
Degi has joined ##openfpga
hitomi2507 has joined ##openfpga
emeb_mac has quit [Quit: Leaving.]
OmniMancer has joined ##openfpga
mumptai has joined ##openfpga
sorear has quit [Read error: Connection reset by peer]
sorear has joined ##openfpga
_florent_ has quit [Ping timeout: 246 seconds]
_florent_ has joined ##openfpga
jeanthom has joined ##openfpga
Asu has joined ##openfpga
mumptai has quit [Remote host closed the connection]
kristianpaul has quit [Read error: Connection reset by peer]
kristianpaul has joined ##openfpga
mumptai has joined ##openfpga
genii has joined ##openfpga
jeanthom has quit [Ping timeout: 240 seconds]
jeanthom has joined ##openfpga
pepijndevos has quit [Ping timeout: 260 seconds]
pepijndevos has joined ##openfpga
<tnt> Posting this here in case someone isn't on 1b2 discord and is interested in ice40 pll dynamic reconfiguration : https://github.com/YosysHQ/icestorm/wiki/iCE40-PLL-documentation
jeanthom has quit [Remote host closed the connection]
jeanthom has joined ##openfpga
kristianpaul has quit [Read error: Connection reset by peer]
kristianpaul has joined ##openfpga
jeanthom has quit [Ping timeout: 258 seconds]
jeanthom has joined ##openfpga
Bike has joined ##openfpga
m4ssi has joined ##openfpga
m4ssi has quit [Remote host closed the connection]
emeb has joined ##openfpga
OmniMancer has quit [Quit: Leaving.]
somlo has quit [Remote host closed the connection]
somlo has joined ##openfpga
mkru has joined ##openfpga
hitomi2507 has quit [Quit: Nettalk6 - www.ntalk.de]
<Finde> is there a common best practice for tool-specific hacks with vhdl? in verilog we'd just use ifdefs based on the simulator/synthesis tool in use
<Finde> not sure what the equivalent is for vhdl
jeanthom has quit [Remote host closed the connection]
jeanthom has joined ##openfpga
<keesj> I think different compilation units / files
mkru has quit [Quit: Leaving]
emeb_mac has joined ##openfpga
jeanthom has quit [Ping timeout: 264 seconds]
kiboneu has quit [Quit: bye]
kiboneu has joined ##openfpga
parport0 has quit [Ping timeout: 240 seconds]
parport0 has joined ##openfpga
mumptai has quit [Quit: Verlassend]
Asu has quit [Ping timeout: 264 seconds]
emeb has quit [Quit: Leaving.]
genii has quit [Quit: See you soon.]