<whitequark>
nextpnr-ecp5 kinda sorta worked but also not quite
<whitequark>
hm
<whitequark>
i don't recall
<daveshah>
it does look a bit like it could be nextpnr doing something dodgy with the clock routing
<ktemkin>
the documentation makes it sound like the Tx and Rx FIFOs are driven from the same clock internally
<ktemkin>
which is either the CDR recovered clock (CHX_SEL_SD_RX_CLK=1) or CHX_FF_EBRD_CLK (CHX_SEL_SD_RX_CLK=0)
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<daveshah>
there is also the 'feedback' thing to make sure the output clock is phase aligned with the fabric clock tree
<ktemkin>
I can't imagine how their described clocking scheme could be conducive to clocking things, since it seems like aligning to the recovered clock changes the point where data's pulled into the Tx FIFO
<ktemkin>
Degi was stuck on avoiding transmit glitches like that for a while; she eventually worked around it by disabling gearing in the SerDes and implementing gearing in the gateware
<daveshah>
Anyway, if you do get Diamond up and running and there is a difference, give me bitstreams from both and I can compare the clock routing
<ktemkin>
will do
<ktemkin>
or, actually, Degi: if you have Diamond licensed using the key that came with your versa, can you try your older commits with gearing in both Trellis and Diamond and send me bitstreams?
<ktemkin>
I'll throw them on the PCIe analyzer
<Degi>
Hm I could try installing diamond again... I think last time it kinda didn't work or I didn't know how to use it
<ktemkin>
Degi: you can message me and we can figure out getting Diamond running; you probably can get to it faster than I can
<Degi>
Also the gearing worked okay-ish and then someday it just stopped working
<Degi>
Okqa
<Degi>
Ill try installing it
<Degi>
*Okay
<ktemkin>
I'm up to my neck in USB3 at the moment; but I'd love to have the SerDes soothed so I can dump the TUSB1310A and switch to configurations people actually want to use ;)
<Degi>
Hm yes... I guess doing soft gearing at 500 MHz would be "suboptimal"
<Degi>
Oh cool, it has a linux version.
<ktemkin>
yeah, it's in the AUR
<ktemkin>
Degi: I already have a layer of gateware gearing from 250MHz down to 125MHz; I don't need another one =P
<Degi>
Hm you could do 500 -> 125 in one
<ktemkin>
I'd rather not =P
<ktemkin>
especially as with a hard PHY the gearing on the 500MHz PIPE signals is handled by DDR I/O to avoid exactly that =P
<Degi>
Hmm
<Degi>
I wonder if you can gain significant performance by overvolting this chip.
<ktemkin>
I don't know at what point inching up the core voltage stops improving performance
<Degi>
Maybe at the point where it catches on fire
<ktemkin>
there’s a point where thermal noise starts skewing metastabilty characteristics; I imagine the timing curve drops off well before catastrophic thermal runaway =P
<Degi>
Wont the gates start failing sometime and then damage the transistors doping?
<ktemkin>
I'd assume that thermal stress would break things well before you'd start e.g. puncturing the gate oxides
<Degi>
hmm
<ktemkin>
but if you've got ECP5s to burn (literally), you're welcome to torture them; I'm sure azonenberg would be willing to help you with physical failure analysis =P
<Degi>
I mean they're like 5 € each... Maybe someday...
<Degi>
Though not sure if I wanna hand-PnP and reflow double sided PCBs just to see when they break
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<Degi>
ktemkin: Do you use soft gearing for DDR?
<Degi>
Ah, is the PIPE signals 1 Gbit
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<daveshah>
ktemkin/Degi: out of curiosity, is the broken 2:1 design public somewhere?
<Degi>
I think test_pcie_serdes_x2.py in the newest commit should show the issue. But you will need a few changes: Change 'from ecp5_pcie.ecp5_serdes_geared_x2 import LatticeECP5PCIeSERDESx2' to 'from ecp5_pcie.ecp5_serdes import LatticeECP5PCIeSERDES' and the mention a few lines below to 'LatticeECP5PCIeSERDES(2)'. (And if you have a Versa, replace all mentions of 'CH0' with 'CH1' in ecp5_serdes.py and attach loopback cables onto the SMA.)
<Degi>
Actually it worked fine but then suddenly it stopped working, like if I sent "a b c d e f g h" I'd get back something like "a c e g b d f h" or similar (not sure about exact length).
<Degi>
I suspected that something on my Versa broke, but maybe I updated prjtrellis and/or nextpnr (I forgot if I did that) and that broke it
<Degi>
I wondered before why many things that worked for me did not work for ktemkin. Now usually things that work for me work for her too (I guess I had an outdated toolchain?)
<Degi>
Later today I'll try out Diamond to see if that fixes the issue. Maybe I can try installing an older version of the toolchain (but that takes a few hours to compile, so I'd rather not)
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<ktemkin>
Degi: if you need me to build you a particular commit, my machine can do it in only a few minutes
<ktemkin>
I can send you an arch package for whatever later
<daveshah>
Not sure if this helps, but I found this geared-SERDES generated by the Diamond wizard from a while ago