<kitten_nb_five>
i am looking at pages 5, 6 and 13
<kitten_nb_five>
on page 13 it is written that tRAC is tCC*(tRCD+CAS latency-1)+tSAC. however this does not work out with the units, as tCC and tRCD are in (nano)seconds but CAS latency is an integer
<kitten_nb_five>
i would get ns² or sth if i follow this formula. can somebody explain where my thinking-error is?
<tnt>
integer is a number of clock cycle
<mwk>
hmm, convert CAS latency to ns by multiplying with clock period I guess?
<tnt>
you need to multiply that by the clock period.
<mwk>
oh wait
<mwk>
the tCC*tRCD part is worrying regardless
<kitten_nb_five>
yeah, exactly. something is wrong there
<tnt>
You need to convert tRCD to a # of clock cycle.
<tnt>
(which will depends of your clock speed)
<mwk>
what is tCC anyway
<tnt>
liek ceil(tRCD / tCC)
<tnt>
tCC is clock period
<mwk>
isn't it just... clock period
jeanthom has joined ##openfpga
<mwk>
then the whole thing would reduce to tRCD + (CAS latency - 1) * tCC + tSAC, right?
<tnt>
No because you need to round up tRCD to an integer # of clock cycle I think.
<tnt>
You need to wait at least tRCD between the ROW ACTIVATE and the READ but that must be an integer number of cycles obviously.
<mwk>
hrm, yes
<mwk>
right
<mwk>
... also tRAC is an emergent property of the system anyway
<mwk>
not a timing constraint you need to implement
<tnt>
yeup.
<kitten_nb_five>
thank you guys (i assume...), i will look at this. i am thinking about implementing a (simple) simulation of this DRAM to check my controller (still in a really early state but i can read and write single locations) for timing violations as i increase frequency and complexity
<kitten_nb_five>
if (if!) i manage to make something decent i will eventually publish it
<tnt>
RAM vendors often provide simulation modles of their chips.
<kitten_nb_five>
yes, but not this vendor / for this IC
<kitten_nb_five>
i checked this already
<tnt>
Right but ... any SDRAM vendor will have compatible chips.
<tnt>
SDRAM is SDRAM ...
<tnt>
just need to find like the micron equivalent chip.
<kitten_nb_five>
uh, thats true. i will look at the micron website
<kitten_nb_five>
but anyway, just for my understanding: with 25MHz == 40ns clock cycle i get tRAC=tCC*(3+2-1)+tSAC=33ns. does this look correct?
<tnt>
No
<tnt>
I mean if tCC is 40 ns ... the result being 33 ns looks invalid.
<tnt>
I get 85 ns
<tnt>
40ns * (1 + 2 - 1) + 5ns
<kitten_nb_five>
uh yes, i was stupid. thank you!
<kitten_nb_five>
ok so micron do not have a SDRAM so small. i will check the stuff that they have for the smallest size == 64Mb