<daveshah>
Good way to troll the '74 series CPU' concept though...
<omnitechnomancer>
Yea, here is my 74 series CPU with one chip that is just the ALU :P
<omnitechnomancer>
Only thing more trolly would be if they released a '74 series CPU chip :P
<omnitechnomancer>
I have been trying to figure out how one would render a SERV based CPU into a reasonable 74 series circuit via Lofty's 74xx-liberty stuff, but the register file interface is a bit confusing and all the existing socs for it assume FPGA like dual port memory (separate read and write ports)
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<sorear>
hear me out here: Williams tube
* omnitechnomancer
googles.
<omnitechnomancer>
Sounds more delicate than desirable :P
<omnitechnomancer>
Could probably make the register file out of some horrible combination of shift registers and muxes
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<tnt>
there are dual port sram :p
<omnitechnomancer>
they are expensive :(
<omnitechnomancer>
I should see how horrible it would be to run a memory interface at twice the clock speed and do the write on even cycles and reads on odd cycles or something
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<sorear>
that's also a very traditional approach
<Lofty>
omnitechnomancer: how brave are you feeling?
<omnitechnomancer>
Why do you ask?
<omnitechnomancer>
Lofty: somewhat but not too much?
<Lofty>
omnitechnomancer: the IDT7142 is a dual-port RAM. But it's also asynchronous, so have fun with timing.
<Lofty>
*IDT7132
<omnitechnomancer>
sounds like it would be just as annoying as just fudging it into one port by running the clock at half rate for the CPU
<omnitechnomancer>
I am not sure what kind of clock speed one could achieve anyway
<sorear>
the apple ii did that
<omnitechnomancer>
The address collision stuff kind of also makes async dual port ram weird
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<Lofty>
omnitechnomancer: ignoring the register file, I could push SERV to 24MHz
<omnitechnomancer>
the core by itself is a relatively small number of 74 series devices too
<omnitechnomancer>
Does RISC-V do okay as full harvard?
<Lofty>
It's single address space
<Lofty>
But it's also SERV, so I don't think the von Neumann bottleneck is much of a problem
<omnitechnomancer>
Yea but SERV has separate I bus and D bus so you could make an actual harvard implementation by having them be entirely separate memories
<Lofty>
I guess?
<omnitechnomancer>
probably would not work very well with RISC-V software though
<Lofty>
You'd have to make sure the I and D address spaces don't overlap
<Lofty>
And it also means you'd probably got to program an EEPROM every time you want to run something
<sorear>
there's nothing in the user ISA which prevents you from having rw- address regions and --x address regions, and you can even configure the mmu that way
<sorear>
and it's pretty good at keeping rodata out of .text
<sorear>
[the gnu toolchain]
<omnitechnomancer>
Lofty: You just have your second 74series SERV attached to the I space RAM for programming :P
<Lofty>
sorear: what's an MMU? Can you eat it?
<Lofty>
/s
<Lofty>
Yeah, I'm pretty sure we can't afford memory protection
<Lofty>
In possibly the most literal sense of "afford"
<omnitechnomancer>
TLB walker in 74 series logic? :P
<omnitechnomancer>
well page-table walker
<sorear>
i didn't say _you_ had to have a mmu
<sorear>
also i don't recommend nomming 68851
<Lofty>
More likely a MIPS-style software TLB
<omnitechnomancer>
Yea though the TLB is still probably pretty big
<omnitechnomancer>
can one make a bit serial TLB 🤔
<sorear>
note that I wasn't the one to propose making a TLB, you were
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<omnitechnomancer>
Or go the: Here is the 74series CPU, and here is the FPGA in the middle for the MMU route
<zyp>
sorear, it's not emitting constant pools at the end of functions?
<omnitechnomancer>
Lofty: one thing I was curious about is what size you get for a serving but with the ram removed and replaced with ports (but all the translation into a ram interface intact), I'll hack up the verilog for this tonight
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