<kbeckmann> daveshah: what do the VCIB_DCU* tiles do in LFE5U-25F ? got curious if the LFE5U devices have some more untapped features.
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<daveshah> kbeckmann: they would be interconnect to the SERDES
<daveshah> Which does exist as other people have measured the ESD diodes on what would be the SERDES pins
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<kbeckmann> ohh...
<kbeckmann> that's interesting
<whitequark> i wonder if you can use that SERDES for something like USB2 which would be way under spec
<tnt> I soldered a non-serdes variant to a serdes ready pcb. First impression is that it seems to be pulling more current than it should. I haven't actually tested if it works at all yet or not though.
<daveshah> tnt: oh very interesting
<clever> whitequark: how would a SERDES block typically deal with changing the direction of flow? and the non-standard usb states where you have high,high or low,low?
<clever> non-differential* i mean
<whitequark> you can disable SERDES TX and termination by configuring it appropriately and enabling power down move
<whitequark> non-standard USB states can be handled because most SERDES let you transmit low-frequency sideband data on the same lines
<whitequark> *non-differential
<clever> and can you get the SERDES RX on the same pair?
<whitequark> well... you can connect them
<whitequark> physically on board
<clever> ah, bit cheaty but as long as reflections dont get out of hand
<tnt> daveshah: of course it's ... 1 sample ... I could also have screwed up something.
<clever> that would probably allow any differential signal, if you can meet the symbol rate, hdmi/dsi/csi/usb/pcie
<whitequark> serdes in 25f are probably not qualified
<whitequark> so USB3 is almost certainly out
<daveshah> ^
<whitequark> as it stretches the capacity of even normal serdes
<daveshah> yeah, most of them might work OK
<clever> whitequark: what about aligning a SERDES RX to an incoming clock preamble?
<daveshah> but some might be really bad
<whitequark> clever: that's just normal serdes operation, no?
<clever> ive not worked with SERDES much yet, mostly just been reading the docs on how the analog-y end works
<whitequark> ah i'm the opposite
<clever> hdmi for example, has 4 differential lanes, the clock lane just runs at the raw pixelclock (min 25mhz), one complete cycle per pixel
<tnt> For USB2 you'd basically be using the serdes as a oversmpler and so cdr in fabric. Not sure preamble would be long enough for CDR.
<clever> but the other 3 lanes (r/g/b) run at 10x that, and use 10/8 encoding
<whitequark> hmmm
<clever> so you need a 10x PLL to lock onto the pixel clock, and the pixel pair doesnt even need a SERDES really
<clever> but, the clock and r/g/b lanes may be different lenghts
<whitequark> pixel pair?
<clever> so you need a PLL with phase-offset taps
<clever> and then you tune each rx (r/g/b) to the right tap, to deal with the delay
<daveshah> You could probably just use an IO running slightly overclocked at 960Mbps to oversample USB 2, tbh
<whitequark> daveshah: the idea was that using SERDES would lower the demands on fabric
<whitequark> unclear if it's a win or a loss
<whitequark> overall
<clever> whitequark: once the 3 rx lanes are tuned, you are getting 30bits per pixel, each channel had 4 special 10bit codes, to signal that its in a blanking period
<tnt> daveshah: heh, usually for soft cdr 4x oversample is what I've seen done.
<clever> whitequark: during that blanking period, after decoding those 4 special symbols, you get 6 bits out (2 per lane), each pixel-time, 2 bits are for hsync/vsync
<daveshah> yeah if you want 4x oversampling then I think the SERDES is the most realistic option
<clever> and during the active period, you have 256 10bit symbols, to map to the 8bit space, for RGB888
<clever> the only funky stuff left, is that during blanking, those special 4 symbols, have a high number of edges, so you can tune the PLL phase-taps
<clever> but during the active period, the 10bit symbols are using some funky accumulator math stuff, to have as few edges as possible
<whitequark> ah
<whitequark> TMDS, right
<clever> i think so
<clever> according to https://www.extron.com/article/dvihdmi_ts, the pixel clock can be anywhere from 25mhz to 600mhz
<clever> and due to the 10x PLL, your raw symbol rate would be 6ghz!!!
<whitequark> ghz or gsps?
<whitequark> i mean, it's 6 gigasymbols per second, but the analog bandwidth is much lower, right?
<clever> gsps maybe?, on every rising edge of the 600mhz clock, you need to have fed 10 bits thru the SERDES
<whitequark> ah in that sense, yeah
<clever> ive been investigating a number of protocols, in my attempt to improve the rpi-open-firmware project
<clever> by understanding hdmi, i can shove a scope into the hdmi port, and understand how "wrong" the signal is, and adjust the drivers to fix it
<clever> ive also been trying to track down the usb-c PD specs, because thats needed to do usb-c hdmi alternate mode
<whitequark> the pd specs are on usb.org
<clever> ive checked, i cant find them there
<clever> https://www.usb.org/usb-charger-pd is missing the finer details
<clever> its mostly overview, and what they test for
<whitequark> because you're looking at marketing and promotional materials
<whitequark> and you should be looking in the document library
<clever> ahh
<clever> why must google fail me so? lol
<whitequark> why are you relying on google? they can barely do search
<whitequark> use your own skill
<clever> i expected the specs to be more closed, like android-auto
<clever> and pci-e i believe
<whitequark> essentially all usb specs are fully open
<whitequark> pci-e specs are widely accessible, eg on https://cloud.whitequark.org/s/cYiwA4Z2YCz4MCa
<whitequark> that includes up to gen5
<clever> i cant remember which protocol it was then
<clever> but i remember a take-down request i saw on wikipedia once, to have the pdf erased from history
<whitequark> probably something related to displays because of all the copyright crap
<whitequark> there are still some HDMI specs i couldn't pirate
<clever> yeah, DSI is a huge mess of NDA's
<whitequark> though most of them are at https://cloud.whitequark.org/s/pC8MqFTjLswstCb
<clever> from what ive been able to find so far, there are 2 layers to usb-c
<whitequark> some DSI specs are at https://cloud.whitequark.org/s/FpjTCn7KLrRpBm6
<clever> the passive layer is just an agreement on pullups and pulldowns
<clever> and depending on which combination of devices you use (and how the cables are flipped), they form different voltage dividers
<clever> that lets a host identify if something is a device
<whitequark> basically
<clever> lets a device identify how many amps it can pull
<clever> and also lets both ends detect if the cable has its own brains (e-marked)
<clever> but the second layer, is an active protocol over one of the CC pins, and is required for hdmi alternate mode
<clever> and i want to implement that on a CM4 module
<whitequark> yep
<whitequark> congratulations! you're about to experience some of the worst pain you'll have in your life
<clever> lol
<clever> ive seen a few chips that deal with PD and requesting higher voltage, but they dont expose the hdmi alt-mode
<clever> so you basically have to re-implement the entire chip first
<whitequark> usb pd takes the process that led to the bad decisions in usb 2 and takes it up to eleven
<whitequark> well, no
<gruetzkopf> can confirm, even trying to implement PD seems to lead to permanent brain damage
<whitequark> you can use something like a tps65982 to request hdmi altmode
<clever> whitequark: most of the chips ive seen so far, also deal with the cable being inserted upsidedown, which i technically dont need
<whitequark> yeah, the host takes care of that
<clever> the hdmi PHY on the pi4 (and CM4), is capable of dealing with full lane swapping
<clever> and one of the hdmi ports on the pi4, is already "mis-wired"
<clever> but the linux driver hides that in the src
<gruetzkopf> you still need to know which order the HS lanes are in
<clever> gruetzkopf: yeah, but via the CC1/CC2 voltage, i can know how the cable is rotated
<gruetzkopf> you don't need to control an external muxer if you know which way the cable is plugged in, true
<clever> and i just have to forward that on to the hdmi driver, and it can swap lanes around
<clever> the pi4 almost did that right
<whitequark> iirc if you use a VDM to request HDMI altmode, the host already knows how to swap the lanes
<clever> the PMIC has 2 adc channels, one is wired to CC1, the other is wired to gnd *facepalm*
<whitequark> i've seen something to that extent in UCSI
<gruetzkopf> i think they're going for implementing the source end
<clever> it seems to be absent in the tps65982, but other PD/hdmi chips ive seen, have an external mux to hide that from the host
<whitequark> tps65982 is not a hdmi chip
<whitequark> it only does pd
<whitequark> (and usb billboard device)
<clever> the last PD chip i looked at, didnt have the ability to even advertise hdmi alt-mode
<whitequark> that's probably a lie
<clever> maybe i didnt read the datasheet close enough
<whitequark> no, i mean, the vendor is lying to you
<whitequark> most of those have a cpu inside
<clever> but i do see alternate modes in the docs, clearly listed for tps65982
<clever> let me check my notes...
<clever> STUSB4500 is what i was looking at earlier
<whitequark> oh ok that one probably cannot indede
<clever> the latest protocl ive been digging into, is android-auto
<clever> basically, its a way for a usb device (your phone) to stream h264 video content to a usb host (the radio in a car), and get touch events back along the same path
<clever> the official android auto app, then renders an android GUI over that h264 stream, and lets you use a very limited set of apps
<whitequark> sounds cursed
<clever> ive found 3 open-source implementations of the radio end of the link
<clever> so you can replace the radio with a pc or tablet
<clever> but ive yet to find an implementation of the phone end
<clever> those DSI docs you linked will probably come in handy later, when i get to that peripheral on the pi
<clever> hdmi/dsi/composite are currently off the table, because of power gating to PLL's
<clever> opensource hw 264 decode is also off the table currently, its using an unknown instruction set on a dedicated DSP, that is specialized for mpeg2/h264 encode/decode
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<pie_> clever: ohai
<clever> *waves*
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<hl> if anyone needs PCIe or MIPI DSI, or other MIPI specs, I've got them: https://www.devever.net/~hl/f/catalogue.txt (grep 'PCI/' or 'MIPI/'). all JEDEC, most of SCSI, ATA too. /msg me if you want anything there
<nats`> better than the usual draft found everywhere ?
<Gracana> Wow, very nice collection.
<mwk> hmm
<mwk> would you happen to know where to find the DFI (DDR-PHY thing) spec?
<hl> aah, DFI
<sorear> why are Z13 and Z14 under POWER?
<hl> sorear: :> yeah it's kind of an 'IBM' directory >_>
<hl> or at least, it turned into that
<mwk> hl: ahhhh many thanks :)
* sorear saves the catalog
<sorear> what I want to read today is a privileged architecture supplement for anything newer than UltraSPARC T2 but it doesn't look like you have one either
<hl> damn, that's obscure
<hl> if oracle isn't publishing the bloody things, my guess is you're screwed
<sorear> the user-level oracle sparc architecture 2015 and 2011 documents are easily findable but leave a lot unanswered about hyperprivileged and mmu stuff
<hl> your only hope is probably to infer stuff from linux/arch/sparc (possibly oracle unbreakable linux's gpl dump, if they haven't been mainlining it, I hear arch/sparc is bitrotting)
<sorear> no arch/sparc/kvm :(
<hl> aw
<hl> if you were _really_ desparate, you could snarf @oracle.com emails from arch/sparc contributors and send a polite email with questions, but, yeah
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