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<clever>
what kind of clock quality does a PLL typically need as an input? is it common to do something like take the hdmi pixel clock, and shove it into a 10x PLL on an fpga?
<clever>
and then the entire input stage (differential decoding and such) operates in a clock domain managed by the hdmi src?
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<tnt>
yes
<clever>
and i'm guessing you would then want some kind of cross-domain fifo, to shift that data into a more stable domain, and some unregistered status, to signal when the pll has lost the lock?
<tnt>
Depends what you're doing with the data really ...
<clever>
are you faimilar with the low-level encoding of hdmi?
<tnt>
I know it exists, I know it's 8b10b but not hte ibm one, they came up with their own tmds thing ... I don't know the math by heart though ...
<clever>
basically, each of the 3 data lanes is ran thru that weird 8b10b encoding, with 256 valid 10bit patterns
<clever>
but during the blanking period, 4 special 10bit patterns are used (not part of the main 256)
<clever>
so during the active area, you get 24 bits per pixel (3 lanes), but during the blanking period, you get 6 bits per pixel
<clever>
the main 256 symbols use some funky math i dont understand, to keep the number of transitions low, for RF/emi reasons
<clever>
but the 4 special symbols where selected to intentionally have a high numebr of transitions, so you can calibrate the inter-lane delays
<clever>
then you just use the phase taps on the 10x PLL, to delay when you sample bits for each lane
<tnt>
yeah, makes sense.
<clever>
one example project i'm thinking of, is to make a custom hdmi rx block, that can record things at a lower level then normal
<clever>
so i can diagnose a mix-configured hdmi tx block
<clever>
mis-configured*
<clever>
the 6 bits/pixel during the blanking period, encodes the hsync/vsync signals, along with some misc stuff like audio and some weird metadata almost nobody uses
<clever>
i believe hdmi has a min pixel-clock of 25mhz, but the final clock depends on the refresh rate and image dimensions, so it can vary a lot
<tnt>
yes
<clever>
main thing i worry about with the above plan, is that my fpga board only has 0.1" headers
<clever>
so id be routing high speed differential signals thru some non-matched 0.1" pins
<clever>
but i can skip the loose jumper wires though, so it wont be that bad
<clever>
as a really basic debug tool, i could just capture the raw 10bit symbols into block ram, and then dump it to the pc, like a basic logic analyzer
<clever>
from reviewing the spartan6 datasheet, it looks like the blockram is all dual-port, so i could easily have one domain driven by the pixelclock*10 feeding data in, then a second domain tied to the uart, reading it out
<clever>
then i just need to manage the mismatch in data-rates, and turn the sampling on/off
<tnt>
jfyi, usually you'd do pixelclock*5 and use DDR IO.
<clever>
ah, i can see how that would work equally well, and then it outputs 2 bits per clock?
<clever>
then i just need a shift register that can shift by 2 per clock, to build up a 10bit symbol?
<tnt>
yes
<clever>
the rest of the logic would then be operating on a 10bit bus, would i clock that from the original pixelclock, or (pixelclock*5)/5 ?
<clever>
i think (pixelclock*5)/5 makes more sense, since it will be aligned to one of the edges of the pixelclock*5 data
<clever>
there must be some latency in the *5 pll?
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<cyrozap>
Here's kind of a random question: Does anyone here know of a memory-mapped UART peripheral that has its RX register at offset 0, TX at offset 1, RX status at offset 5, and TX status at offset 6? It's not an 8250/16550, since that combines the TX and RX registers into a single register and it does the same with the TX and RX statuses.
<cyrozap>
The context is that I'm trying to reverse engineer the memory-mapped UART of an 8051-based chip.
<tnt>
no, but I can make one real quick :)
<clever>
tnt: that gives me a weird idea, a kind of verilog compare util, where i write an implementation of X, and then have the util search for other implementations of a similar device
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<cyrozap>
clever: That sounds similar to the kind of function signature matching that Ghidra and IDA can do.
<clever>
cyrozap: ive not seen that in ghidra yet, but it sounds very useful
<clever>
ive been having to manually compare functions
<clever>
cyrozap: where is it hidden in the ghidra ui?
<cyrozap>
clever: In the code browser, click File->Configure then click the checkbox next to "Function ID". This will cause a "Function ID" submenu to appear under the "Tools" menu.
<cyrozap>
Why this is disabled by default, I have no idea.
<cyrozap>
But I found out how to enable it by searching for "function ID" in Ghidra's built-in manual.
<clever>
cyrozap: another crazy thing, i ran out of disk space one day, and EVERY SINGLE thing in file->configure turned itself off
<clever>
it didnt even look like the same program after that
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<clever>
i also dont have functionid, just callgraph/comparison/tag/signature, function signature decompiler hover plugin??
<cyrozap>
clever: I'm on the master branch with some PRs merged. But I think the Function ID stuff has been around for a while.
<clever>
*doh*
<clever>
it was file->configure, not file->configure->configure
<cyrozap>
lol yeah, sorry for the the confusion.
<clever>
na, your directions where perfect
<clever>
i went off the trail because i knew of that ui from past problems
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<clever>
ok, found a memset, that should be a good target
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<clever>
cyrozap: how do i use it?
* clever
reads "function id" in internal help...
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<clever>
cyrozap: ahhh, this is likely why it wants to know if it was gcc or visual-studio, at import time
<clever>
to pick the right functionid db for labeling things
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<clever>
cyrozap: cant seem to get it to re-match against already analyzed files though...
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<clever>
ah, i can analysis->oneshot->functionid
<clever>
cyrozap: that just leaves my unfinished RE'ing, large chunks of functions just say "vl805" now, because i havent found what they do yet
<clever>
cyrozap: ooooo, i have an old .elf they forgot to strip, a goldmine to populate functionid!
<clever>
cyrozap: ive also got an anoying issue, the .text on this platform, has string constants after the opcodes for each function, so i cant just blanked decode all of .text as opcodes, and ghidra is leaving a lot un-decoded, know of any tricks there?
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<cyrozap>
> large chunks of functions just say "vl805" now