<vup>
scientes: you can do pretty much everything without IP / verilog, just some things cause more pain than others (for example memory interface generated by the IP blocks use things like undocumented PHASER primitives...)
<vup>
s/verilog/with just verilog/
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<_whitenotifier-f>
[libfx2] theedge456 commented on issue #5: i2c bus scan - https://git.io/JklnT
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<_whitenotifier-f>
[libfx2] whitequark commented on issue #5: i2c bus scan - https://git.io/Jklcm
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