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<scientes> when i try to install 2020.1 I get "this OS not supported" because I am running latest Ubuntu and not LTS, and then I get Exception in thread "main" java.lang.IllegalStateException: no splash screen available
<scientes> and then nothing
<scientes> ugghhhh
<scientes> If I get arty board can I learn totally with the free tools?
<scientes> I have LiteFury but I haven't been able to get anywhere, and get to the point that it is fun.
<_whitenotifier-f> [libfx2] theedge456 commented on issue #5: i2c bus scan - https://git.io/JkcJ6
<vup> scientes: the batch install worked for me
<vup> (While getting the same error when trying the gui install)
<_whitenotifier-f> [libfx2] whitequark commented on issue #5: i2c bus scan - https://git.io/JkcUS
<scientes> ERROR: There is not enough disk space on /tools/Xilinx to install.
<scientes> I have 58GB available
<scientes> ugh
<keesj> sometimes also can use strace to figure out why the install is failing
<q3k> 58GB might not be enough :P
<scientes> it would be much more if the installer wasn't so huge
<vup> Do you have 58GB on / ?
<scientes> yes
<scientes> except /boot
<keesj> That makes the tools cheaper per MB
<vup> My install has ~35 GB so that should work
<omnitechnomancer> I think 2017 is smaller
<keesj> idem here (34G)
<keesj> so.. you need double to install ?? download + extrated size
<vup> yeah the installer first downloads everything and then unpacks everything, so that might be it
<whitequark> ... i thought the web installer would do a streaming unpack, specifically to avoid this
<cyrozap> whitequark: Do you remember what version of boolector you uses when you did this? https://lab.whitequark.org/notes/2020-04-06/synthesizing-optimal-8051-code/
<whitequark> nope
<whitequark> probably 3.1.0
<cyrozap> Oh, interesting. I'm using 3.2.0 and Rosette is complaining about "unrecognized solver output". Guess I'll have to learn some Racket...
<implr> scientes: for 'os not supported' fake being a redhat
<implr> batch install works but is annoying
<implr> 1319-18:42 < implr> CentOS Linux release 7.6.2003 (Core)
<implr> 1318:18:42 < implr> # cat /etc/redhat-release
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<scientes> oh wow, 71GB required
<scientes> its bigger than all the other software on my computer combined
<scientes> nice hack though, worked
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<_whitenotifier-f> [libfx2] theedge456 commented on issue #5: i2c bus scan - https://git.io/Jkc00
<_whitenotifier-f> [libfx2] whitequark commented on issue #5: i2c bus scan - https://git.io/JkcER
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<scientes> so I get this NiteFury board, and it has to tell you that it has to work around bugs in Vivado
<scientes> > The usual way to override autogenerated constraints is to simply put new constraints in a different file, and have have those constraints take effect later
<scientes> by changing the PROCESSING_ORDER property of the file. See [https://www.xilinx.com/support/answers/52947.html].
<scientes> > However, the LOC property, which is the one we need to change, doesn't work in this fashion, since Vivado can't assign a LOC property to a cell
<scientes> if the LOC is already in use. And they are all in use. Normally, the reset_property function can fix this, but reset_property doesn't work in constraint files.
<scientes> Uhhhh, I feel like I am programming windows
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<Finde> scientes: given I always expect (critical) warnings from vivado that note was perplexing to me haha
<scientes> I am just a software guy trying to get to the place when FPGAs are fun.
<Finde> unfortunately vivado is routinely an impediment in that
<scientes> yeah I am getting that impression
<scientes> the hardware clearly is awesome
<scientes> (as soon as I can use it)
<Finde> yeah I didn't realise I needed the JTAG cable when I ordered mine
<Finde> luckily it only took a few days to get one shipped
<scientes> I haven't even gotten that far
<scientes> I got a fomu, and the FPGA is hooked up to the USB pins which makes it not very user friendly
<Finde> a couple of things to watch out for (I did it last week): I'd use the xilinx upstream repo for the xdma driver rather than what's packaged in the nitefury repo since it wasn't compiling for me on a newer kernel
<scientes> and now I have this LiteFury, which hardware wire should be great
<scientes> Finde, do you have a set of instructions that "just works"?
<Finde> and make sure to install the xilinx cable drivers or else your jtag cable will show up but not be usable by vivado
<scientes> I am not not resourceful, but I need a starting place that works.
<Finde> I cloned the repo you have above, opened the .xci in vivado gui and hit "generate bitstream" so it ran all the steps
<scientes> Like with software, you can just take anything apart that you see, but for FPGAs the examples are jokes.
<Finde> and produced a .bit in impl_1/
<scientes> yeah it didn't want to produce a .bit for me
<scientes> complained about out-of-date IP, and threw warnings
<Finde> hm it should autoupgrade the ip
<scientes> and I am like "I don't want any IP--I want free software"
<Finde> you can select all the IP in the window that lists them and just tell it to synthesise them I think
<scientes> OK, great though to hear someone here has success with litefuryt
<scientes> mine is the SQRL 215+
<Finde> do you have a cable for programming it?
<scientes> it is m.2......
<scientes> i thought i just plug it in
<Finde> I was unclear on that... I ended up buying the cable but it could've just been my mistake
<scientes> like a arty board, sure
<Finde> I saw some people saying there's no onboard jtag for nitefury
<Finde> but the google results were a bit sparse
<scientes> it does have a JTAG port
<Finde> could be worth just installing the cable drivers from vivado and seeing if a programmable device shows up or not
<scientes> it shows up on my pcie bus
<scientes> also the fan is annoying
<scientes> as it runs at 100% all the time
<Finde> it's really prodigious isn't it
<scientes> instead of heat-sensitive
<scientes> I unplugged it until I get a .bit file, assuming the only reason it got hot when i stopped the fan was that it had some stupid bitcoin software installed
<scientes> what JTAG cable are you using?
<Finde> digilent hs2
<scientes> that is almost as expensive as the board
<Finde> yeah again I'm not totally sure I needed it but in my case I'll be using it for other things so I just picked it up
<scientes> Note:
<scientes> This cable is not needed for Digilent FPGA boards as our boards are designed with this functionality natively.
<Finde> the header on that board is the same as comes with the little cable in the litefury box
<scientes> mine had no cable
<Finde> ah well that's more complicated
<scientes> mine is the SQRL-215+ which is the same board, but was sold for bitcoin mining
<Finde> why help anyone field program their gate array if they just want to mine
<scientes> I have no interest in mining
<Finde> right
<scientes> they are cheap because bitcoin is a very silly idea
<Finde> see "Can I load my own bitstreams on Acorn? How do I develop for Acorn?"
<Finde> can't say I've found this step-by-step tutorial
<scientes> lame
<scientes> double-lame that you need a JTAG cable
<Finde> I imagine there are significantly cheaper alternatives to the one I got
<Finde> but there's still that pico ezmate cable issue
<Finde> mine came with a pico ezmate to xilinx jtag adapter cable
<Finde> I suppose because I picked up the litefury from rhs research directly
<vup> if you have a rpi you can also use this: https://github.com/derekmulcahy/xvcpi
<vup> (or use that as inspiration to implement a equivalent for your favourite rpi alternative)
<scientes> vup, this board is m.2 only. there is no ethernet port
<scientes> oh
<scientes> The xvcpi server runs on a Raspberry Pi which is connected, using JTAG, to the target device. Xvcpi bitbangs the JTAG control signals on the Pi pins. The bitbanging code was originally extracted from OpenOCD.
<vup> yes, it emulates a xilinx virtual cable, xilinx's version of remote programming
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<implr> scientes: you can also buy a fake xilinx usb cable on ebay/aliexpress
<implr> they were ~$30 when i got mine
<implr> (as opposed to >200 for the original)
<scientes> still kinda pissed about getting duped
<scientes> yeah $25, but shipping from china is SLOW
<scientes> maybe i can send it to my remailer IN china
<scientes> even though that is not really how eBay works
<scientes> but there are so many of them
<scientes> I have no idea which one will work
<scientes> CPLD?
<implr> they're universal for eveyrthing xilinx
<implr> btw i'm also waiting for a sqrl in the mail, iirc there was some open documentation
<scientes> i didn't find any documentation
<scientes> it doesn't have pins
<scientes> maybe i should take picture
<scientes> its small cause its on m.2 card
<scientes> its also on bottom....
<scientes> but cord goes off to side
<whitequark> you can program FPGAs with just about anything if you ask Vivado to generate an SVF file
<implr> ah, the connector on the acorn
<whitequark> a $3 FTDI dongle works just fine
<implr> is not standard
<whitequark> you don't need the xilinx cable
<implr> the ribbon cables you get with the xilinx cables are sorta standard
<implr> whitequark: still useful if you want to jtag a zynq or use ILA
<scientes> whitequark, yeah looked like FTDI to me, that is why I kept asking questions....
<scientes> but openfpga has no support for zynq
<scientes> or does it?
<mithro> @scientes FYI - PrjXray has support for Zynq
<scientes> cool
<scientes> are there any ASMP FPGA layouts, like with real CPUs on the same memory bus as the FPGA and a way to do syncronization?
<implr> there's the ACP port in the zynq, which hangs off the l2 cache in the arm
<implr> and is coherent
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<Finde> is that ACP accessible?
<vup> yes you can access it from the fpga via a axi port
<Finde> is there much documentation on this?
<Finde> hm that might disallow what I was thinking of then
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<scientes> it would also mean that I wouldn't need to use any IP
<scientes> cause everything could be in verilog
<implr> there are some appnotes from xilinx
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<scientes> all these walk-throughs of GUIs.....
<implr> yeah xilinx appnotes are generally like that
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