kristianpaul has quit [Read error: Connection reset by peer]
kristianpaul has joined ##openfpga
Asuu has quit [Quit: Konversation terminated!]
mumptai has quit [Quit: Verlassend]
Degi has quit [Ping timeout: 240 seconds]
Degi has joined ##openfpga
emeb has quit [Quit: Leaving.]
<cyrozap>
Heh, so apparently my RV32I-on-8051 emulator isn't as fast as I thought, and I was just running it on a _very_ fast 8051 (ASMedia xHCI USB host controller). I ported my RISC-V code over to an old RTD2660/RTD2662 board I had laying around (LCD controller chip), and wow, it's _slow_. Like, the serial port's running at 115200 8N1, but I can see each individual character being printed on the console.
<cyrozap>
Looking at it with a logic analyzer, the "effective" bitrate is closer to 2400 bps. But of course, this RTD266x chip is running at 27 MHz, and it's using Synopsys's DW8051 which runs at a minimum of 4 clock cycles per instruction. In contrast, the ASMedia ASM1142 runs at 78 MHz and most likely executes single-byte instructions in a single clock cycle.
forrestv has quit [Ping timeout: 268 seconds]
forrestv has joined ##openfpga
ym has joined ##openfpga
emeb_mac has quit [Quit: Leaving.]
forrestv has quit [Ping timeout: 260 seconds]
<TD-Linux>
obviously your next goal should be to hunt down the fastest superscalar 8051 implementation you can find
forrestv has joined ##openfpga
forrestv has quit [Ping timeout: 260 seconds]
<cyrozap>
Yeah, I was half-jokingly considering designing one a while ago. Maybe I should actually do it, and then submit it to that Efabless/Skywater/Google free ASIC thing. Though it'd have to be designed, laid out, and tested within a week, since the deadline's the 30th, lol :P
forrestv has joined ##openfpga
<Ultrasauce>
sounds like a plan to me
sgstair_ has joined ##openfpga
sgstair has quit [Ping timeout: 260 seconds]
<cyrozap>
Just in case it wasn't clear, that was a joke--there's no way I'd even finish the design in a week, let alone write all the testbenches for it and figure out the ASIC toolchain on top of that.
jeanthom has joined ##openfpga
<cyrozap>
I'm half tempted to submit something stuipd, like a PWM + state machine that just continuously plays a meme song.
<implr>
iirc they wanted to do ~2 runs per year? or something like that
<implr>
so you can always shoot for the next one
<cyrozap>
But by then most people will have their projects ready, and so there will be a lot more competition for space. :(
<cyrozap>
And I think I'm sort of burnt out on hardware design. The actual design part is fun, but writing all the testbenches to make sure things work is such a drag and sucks all the joy out of the process for me, especially when I can't for the life of me figure out what I did wrong.
<TD-Linux>
I know that feel, that's why so many of my projects take forever. it's not so bad once I can get myself in the zone
<TD-Linux>
doing a superscalar cpu would be fun, but also I really don't know anything about the design. I'd like to design a fast 68k core
laintoo has quit [Read error: Connection reset by peer]
<TD-Linux>
I'm currently clocking up ao68000 on a ecp5. it's a pretty cute design, with a java microcode generator
<TD-Linux>
the microcode features branches and a call stack
mumptai has joined ##openfpga
jeanthom has quit [Ping timeout: 256 seconds]
laintoo has joined ##openfpga
sgstair_ is now known as sgstair
Asu has joined ##openfpga
Asu has quit [Remote host closed the connection]
Asu has joined ##openfpga
<TD-Linux>
love the new gtkwave that makes my eyes bleed at hidpi
<TD-Linux>
oh it's because my distro rebuilt it with gtk3