00:22 <awygle> hey gang, i'm giving away some dev boards this December for folks who don't feel they can justify spending the money on them. if that's you, or you want to contribute, or you want to signal boost, please check it out: https://twitter.com/awygle/status/1333923834194325504

01:08 <Zorix> that's really nice of you!

01:37 <awygle> just trying to give back a little :)

02:07 <Zorix> I have the icebreaker, but unfortunately I haven't started to play with it yet, been waiting for the tools to mature more as well.. at least thats the excuse for my laziness

02:52 <notafile> well I can tell you, I bought a better supported board and it did not help ;)

02:53 <Zorix> oh?

02:58 <kc8apf> I have quite a few top-notch dev boards from Altera, Xilinx, and Lattice. Getting any of them to work is a frustrating exercise

03:27 <azonenberg> kc8apf: what kind of issues have you had with xilinx boards?

03:37 <kc8apf> Convincing ISE or Vivado to install, remembering to install udev scripts, everything about iMPACT, missing or incorrect pin constraints, broken examples

03:39 <azonenberg> The only vivado i've ever had problems installing is 2020.1, which has some broken version detection that works on their "supported" OSes but not on debian

03:39 <azonenberg> the ftdi based digilent jtag dongles i have worked out of the box completely painlessly

03:39 <azonenberg> cant comment on vendor pin constraint files as i've never built any of the example designs

03:40 <azonenberg> i always write my own constraints off the published pdf schematics

03:40 <azonenberg> in general the boards have treated me fine

03:41 <azonenberg> My xilinx problems have been more along the lines of "vivado segfaults when launching a simulation 1% of the time"

03:41 <azonenberg> or "ISE's placer was absolute garbage and required heavy floorplanning to make timing on most designs that pushed limits in any way"

03:42 <tpw_rules> ooh i need to get back into suffering as a consequence of that

03:42 <azonenberg> I've found documentation errors, but i've done that with everyone

03:42 <azonenberg> in fact, i set a new personal record

03:42 <azonenberg> my new 4 GHz active differential probe hasn't even arrived in my lab yet

03:42 <azonenberg> and i already am responsible for a datasheet revision :p

03:43 <azonenberg> Usually i have to get my hands on the product before finding mistakes in the documentation lol

04:51 <kc8apf> Digilent boards are usually ok. Some of the other Xilinx boards use FTDI for JTAG but use a different pinout so Xilinx tools won't work.

05:35 <Finde> god that vivado version detection

05:35 <Finde> I had to replace my /etc/os-release with one from an ubuntu machine to complete the install

06:07 <etrig> ./xsetup -c ~/.Xilinx/install_config.txt --agree XilinxEULA,3rdPartyEULA,WebTalkTerms --batch RegretLifeChoices

06:27 <implr> yeah batch works, but if you later want updates via xic you need to pretend to be a redhat or old ubuntu anyway

06:27 <implr> also i've poked at that thing with a debugger

06:27 <implr> and i'm 80% sure the problem is in the *warning dialog itself*

06:28 <implr> which does some dumb java gui crash and blocks the main window from appearing

15:49 <azonenberg> implr: i'm 95% sure that's what it is

15:49 <azonenberg> i looked into it a bit

15:49 <azonenberg> then just did an offline install because i was sick of dealing with it