20:30 <agg> does anyone know of any documentation for the ecp5 (or other lattice fpga) spi passthrough jtag mode?

20:31 <agg> it's been working basically fine for me but i'm now finding the spi clk seems to go hi-z before cs is de-asserted in a way that's quite unhelpful/glitches

20:34 <daveshah> I don't think the behaviour is formally documented anywhere

20:34 <daveshah> It was RE'd from the SVF files that Diamond generates

20:35 <daveshah> I know we have seen dubious behaviour on the Nexus parts, so perhaps that is related

20:36 <agg> shame as it's such a convenient feature

20:36 <agg> i'll keep poking, maybe a change of idle polarity will help or something

20:39 <daveshah> I'm wrong, it is briefly documented for the Nexus here: http://www.latticesemi.com/view_document?document_id=52790 (p43)

20:40 <daveshah> not much detail, and although Nexus is pretty similar to ECP5 I wouldn't be surprised if the exact timing relationships changed a bit

20:41 <agg> oh, thanks! better than nothing

20:41 <agg> I think I saw the JTAG IR command for it mentioned in some older docs too but without any further elaboration

22:50 <cr1901_modern> >It was RE'd from the SVF files that Diamond generates

22:50 <cr1901_modern> This is how Luke/tinyfpga created tinyproga as well

22:51 <cr1901_modern> Docs sadly aren't enough