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<mwk> ... so remember when I said that at least Xilinx documentation doesn't suck as much as other vendors'?
<mwk> I'd like to retract that with Versal
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<daveshah> The move is very much to 'use the pretty wizard and be happy'
<mwk> I hoped I could at least understand how the CLB works and see if a quick patch to yosys is viable
<mwk> but it seems the documentation is now intel quality level
<mwk> and the sim models don't make fucking sense
<mwk> like, the LUT primitives have unused outputs?!?
<mwk> and it's still not clear to me how the LUTs connect to LOOKAHEAD8
<mwk> // Parameter encodings and registers localparam LOOKB_FALSE = 0; localparam LOOKB_TRUE = 1;
<mwk> localparam LOOKD_FALSE = 0;
<mwk> localparam LOOKD_TRUE = 1;
<mwk> repeat for more letters
<mwk> perfect coding style, Xilinx, exactly what I expected from a sim model
<daveshah> Ugh, the Lattice sim models always seem to be written in the most annoying way possible
<implr> lookd,,,
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