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<sensille>
yosys ecp5 bram infer again ... i get "Read port #0 is in clock domain !~async~." and i can't find out why
<sensille>
the output is registered and the address input is also directly from a register
<daveshah>
Do you have an initial value or reset on the output?
<daveshah>
Neither of those are supported currently
<sensille>
no
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<sensille>
registering the rptr a second time helps
<sensille>
but i don't get why this is only in one instance a problem. i use the same module several times without problems
<sensille>
does it need 2 clocks to provide the data?
<tnt>
No
<sensille>
isn't that enough? always @(posedge clk) dout <= ram[rdptr];
<sensille>
where rdptr is a register
<daveshah>
yeah, that's fine even if rdptr isn't a register
<daveshah>
I suspect that some optimisation pass is spoiling the pattern that memory inference needs
<sensille>
if i insert another register before rdptr it works
<sensille>
(which i don't want to do)
<tnt>
Try adding (* keep *) on rdptr
<sensille>
still Read port #0 is in clock domain !~async~.
<whitequark>
by this point you could probably just instantiate $memrd...
<whitequark>
actually i'm not sure if that works from verilog
<sensille>
hah, (*keep*) on dout helps
<daveshah>
are you not using some bits of it?
<sensille>
maybe i missed one
<daveshah>
i've just remembered that this is/was an issue in Yosys, if some bits of the memory output are unused then the dff gets swept away and then the read port looks async
<sensille>
correct, i missed one bit. now it works without keep
<sensille>
so it found a bug in the design
<sensille>
although i'd prefer a more direct error message ;)
<sensille>
thanks for the hint
<daveshah>
it's not an error at all, it should be able to map it correctly
<sensille>
... or a warning
<sensille>
but sure, it could just as well be intentional