Topic for #homecmos is now Homebrew CMOS and MEMS foundry design | http://code.google.com/p/homecmos/ | Logs: http://en.qi-hardware.com/homecmos-logs/
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<B0101> hey azonenberg
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<azonenberg> Back, was visiting family for christmas
<azonenberg> starting up experiments again for the new year :)
<smeding> hey, man
<smeding> merry belated christmas and such
<azonenberg> ty
* smeding is doing some hardware dev of his own
<smeding> the laser projector project, still
<azonenberg> very nice
<azonenberg> brb
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<wolfspra1l> smeding: another laser projector? :-)
<wolfspra1l> I've heard of marcan's openlase project before
<wolfspra1l> does yours have a homepage?
<azonenberg> I am going to be aggressively pushing lithography resolution in the near future
<azonenberg> i want to hit submicron
<azonenberg> even if only in PoC scale tests
<lekernel> azonenberg: you should try to start with things like diffraction gratings... should be relatively easy
<lekernel> and you can make fun ones, like those things you can put on laser pointers to project all sorts of shapes
<azonenberg> lekernel: I know
<azonenberg> thats the goal
<azonenberg> i want to make an optical-wavelength diffraction grating
<azonenberg> probably reflective
<azonenberg> Evaporate nickel or chrome onto a bunch of microscope slides
<azonenberg> then do litho
<azonenberg> I'm going to get a "real" mask as that's been my limit in the past
<lekernel> what materials do they use for the laser pointer thingies?
<lekernel> would be fun to make your own
<azonenberg> send the GDS over to a place like laserlab and have them send me 8000DPI film masks
<azonenberg> That will give me 12.5um design rules and a 3.125um lambda
<azonenberg> Times 4/10/40x reduction with my objectives
<azonenberg> should be easily enough to hit submicron
<azonenberg> I do question whether 12.5um might be too small to resolve on the mask side, i might have to make my design rule be more like 25 or 50
<azonenberg> But there's only one way to find out
<azonenberg> The mask will cost me around $100 and be 10x16 inches usable area
<azonenberg> so i'm gonna tile a mix of 2" contact masks and projection masks of various feature sizes
<azonenberg> including test patterns and probably some comb drive stuff
<smeding> wolfspra1l: nope, mine mostly doesn't exist yet
<smeding> might not even bother with building the hardware
<smeding> my UART for it won't work though :(
<smeding> i'm writing VHDL, it's to familiarise myself with digital signal processing more
<azonenberg> i see
<azonenberg> And yeah a UART is a little slow for that kind of bandwidth
<azonenberg> you'd be better off with USB
<azonenberg> and ideally, feed the GDS into the FPGA over USB and have it do rasterization onboard
<azonenberg> so as to avoid the 480Mbps bottleneck
<azonenberg> Of course at that point you're basically writing a 2D GPU
<azonenberg> Which is, to say the least, a nontrivial task
<smeding> eh, i'm not going for many points/second at first
<smeding> it will be a vector display
<azonenberg> Oh
<azonenberg> So you rent doing it for direct-write litho?
<smeding> eh? this is just for playing
<smeding> :p
<azonenberg> arent*
<smeding> nonono
<smeding> this is pretty much a toy
<azonenberg> Because i want to build a laser system using a bluray diode for doing lithography lol
<smeding> i doubt you can use my code :p
<azonenberg> lol
<smeding> this is kind of the wrong channel for it, i suppose
<smeding> but yeah, it's a toy -- PID loops in digital hardware to drive two galvos to scan a laser beam
<azonenberg> I see
<azonenberg> I'd be doing basically the same thing
<azonenberg> Except trying for much higher tolerances
<azonenberg> so i can get ~20 micron resolution
<azonenberg> Might need some optics but we'll see
<smeding> yeah, nice
<smeding> this is just my foray into tinkering with DSP
<smeding> i'm not quite sure how to do the actual control loop yet... i wrote the dinky motor driver and ADC readout modules
<azonenberg> i see
<azonenberg> I'm going to try for tens of MHz data rate if not better
<azonenberg> ideally more like 100
<azonenberg> as in 100Mpps
<azonenberg> which, on a scanning apparatus, should let me cover a small field (1cm^2) in a decent time
<smeding> then i wrote a FIFO and now i'm working on a UART to hook to that
<azonenberg> i see
<smeding> then, the PID controller and the main controller that loads points from memory and presents them to the control loops
<smeding> and can write from the uart-fifo to memory
<smeding> but currently i have a silly error in my VHDL somewhere, but i can't see where and ISim won't tell me
<azonenberg> how so?
<smeding> it just tells me what VHDL process is in
<smeding> it's the process that generates the new state data for the sort-of-state-machine
<smeding> well, state machine, but not evidently so
<smeding> it's pretty big (and probably inefficient)
<azonenberg> If you want to see a nice simple uart in verilog, i wrote one i use in a couple of projects
<azonenberg> no fifo, this is just the raw uart
<smeding> i should have one in VHDL somewhere
<smeding> but where's the fun in that
<azonenberg> It's <200 lines
<smeding> yeah so's this
<smeding> 123 lines
<azonenberg> Mine is 193 but pretty heavy commenting
<azonenberg> It's also instrumented to log bytes to the console
<azonenberg> So if you want to compare the two and see where they differe feel free
<azonenberg> this is FPGA proven in a spartan-3a at 20.48 MHz while talking to an FT232
<azonenberg> at 115200 baud
<smeding> oh, mine is just the rx side actually
<azonenberg> Well this plays fine in TX mode too if you want to generate a waveform to test against
<smeding> and probably overly complicated
<azonenberg> Yours or mine?
<smeding> mine
<smeding> yours seems sane enough
<azonenberg> Mine is pretty simple, the one complex feature i added was samplnig 90 degrees out of phase
<azonenberg> to avoid any settling issues on the signal edge
<smeding> yeah
<azonenberg> i instead wait half a bit period
<smeding> mine samples thrice
<smeding> and does best of 3
<azonenberg> Thats the alternate option
<smeding> i felt like overcomplicating
<azonenberg> also, mine allows runtime changing of baud rate
<smeding> neat
<azonenberg> though i usually synthesize it with a constant since i dont need to change it
<azonenberg> and it optimizes out a few gates
<smeding> i'll brb
<smeding> have to walk the dog
<azonenberg> But theoretically as long as clkdiv does not change while a character is on the wire (in either direction) it should handle changing fine
<smeding> back
<smeding> actually i had been for a while
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