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<
B0101>
hey azonenberg
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azonenberg>
Back, was visiting family for christmas
<
azonenberg>
starting up experiments again for the new year :)
<
smeding>
merry belated christmas and such
* smeding
is doing some hardware dev of his own
<
smeding>
the laser projector project, still
<
azonenberg>
very nice
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wolfspra1l>
smeding: another laser projector? :-)
<
wolfspra1l>
I've heard of marcan's openlase project before
<
wolfspra1l>
does yours have a homepage?
<
azonenberg>
I am going to be aggressively pushing lithography resolution in the near future
<
azonenberg>
i want to hit submicron
<
azonenberg>
even if only in PoC scale tests
<
lekernel>
azonenberg: you should try to start with things like diffraction gratings... should be relatively easy
<
lekernel>
and you can make fun ones, like those things you can put on laser pointers to project all sorts of shapes
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azonenberg>
lekernel: I know
<
azonenberg>
thats the goal
<
azonenberg>
i want to make an optical-wavelength diffraction grating
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azonenberg>
probably reflective
<
azonenberg>
Evaporate nickel or chrome onto a bunch of microscope slides
<
azonenberg>
then do litho
<
azonenberg>
I'm going to get a "real" mask as that's been my limit in the past
<
lekernel>
what materials do they use for the laser pointer thingies?
<
lekernel>
would be fun to make your own
<
azonenberg>
send the GDS over to a place like laserlab and have them send me 8000DPI film masks
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azonenberg>
That will give me 12.5um design rules and a 3.125um lambda
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azonenberg>
Times 4/10/40x reduction with my objectives
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azonenberg>
should be easily enough to hit submicron
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azonenberg>
I do question whether 12.5um might be too small to resolve on the mask side, i might have to make my design rule be more like 25 or 50
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azonenberg>
But there's only one way to find out
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azonenberg>
The mask will cost me around $100 and be 10x16 inches usable area
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azonenberg>
so i'm gonna tile a mix of 2" contact masks and projection masks of various feature sizes
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azonenberg>
including test patterns and probably some comb drive stuff
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smeding>
wolfspra1l: nope, mine mostly doesn't exist yet
<
smeding>
might not even bother with building the hardware
<
smeding>
my UART for it won't work though :(
<
smeding>
i'm writing VHDL, it's to familiarise myself with digital signal processing more
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azonenberg>
And yeah a UART is a little slow for that kind of bandwidth
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azonenberg>
you'd be better off with USB
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azonenberg>
and ideally, feed the GDS into the FPGA over USB and have it do rasterization onboard
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azonenberg>
so as to avoid the 480Mbps bottleneck
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azonenberg>
Of course at that point you're basically writing a 2D GPU
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azonenberg>
Which is, to say the least, a nontrivial task
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smeding>
eh, i'm not going for many points/second at first
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smeding>
it will be a vector display
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azonenberg>
So you rent doing it for direct-write litho?
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smeding>
eh? this is just for playing
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azonenberg>
arent*
<
smeding>
this is pretty much a toy
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azonenberg>
Because i want to build a laser system using a bluray diode for doing lithography lol
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smeding>
i doubt you can use my code :p
<
smeding>
this is kind of the wrong channel for it, i suppose
<
smeding>
but yeah, it's a toy -- PID loops in digital hardware to drive two galvos to scan a laser beam
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azonenberg>
I'd be doing basically the same thing
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azonenberg>
Except trying for much higher tolerances
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azonenberg>
so i can get ~20 micron resolution
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azonenberg>
Might need some optics but we'll see
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smeding>
yeah, nice
<
smeding>
this is just my foray into tinkering with DSP
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smeding>
i'm not quite sure how to do the actual control loop yet... i wrote the dinky motor driver and ADC readout modules
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azonenberg>
I'm going to try for tens of MHz data rate if not better
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azonenberg>
ideally more like 100
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azonenberg>
as in 100Mpps
<
azonenberg>
which, on a scanning apparatus, should let me cover a small field (1cm^2) in a decent time
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smeding>
then i wrote a FIFO and now i'm working on a UART to hook to that
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smeding>
then, the PID controller and the main controller that loads points from memory and presents them to the control loops
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smeding>
and can write from the uart-fifo to memory
<
smeding>
but currently i have a silly error in my VHDL somewhere, but i can't see where and ISim won't tell me
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azonenberg>
how so?
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smeding>
it just tells me what VHDL process is in
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smeding>
it's the process that generates the new state data for the sort-of-state-machine
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smeding>
well, state machine, but not evidently so
<
smeding>
it's pretty big (and probably inefficient)
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azonenberg>
If you want to see a nice simple uart in verilog, i wrote one i use in a couple of projects
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azonenberg>
no fifo, this is just the raw uart
<
smeding>
i should have one in VHDL somewhere
<
smeding>
but where's the fun in that
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azonenberg>
It's <200 lines
<
smeding>
yeah so's this
<
smeding>
123 lines
<
azonenberg>
Mine is 193 but pretty heavy commenting
<
azonenberg>
It's also instrumented to log bytes to the console
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azonenberg>
So if you want to compare the two and see where they differe feel free
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azonenberg>
this is FPGA proven in a spartan-3a at 20.48 MHz while talking to an FT232
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azonenberg>
at 115200 baud
<
smeding>
oh, mine is just the rx side actually
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azonenberg>
Well this plays fine in TX mode too if you want to generate a waveform to test against
<
smeding>
and probably overly complicated
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azonenberg>
Yours or mine?
<
smeding>
yours seems sane enough
<
azonenberg>
Mine is pretty simple, the one complex feature i added was samplnig 90 degrees out of phase
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azonenberg>
to avoid any settling issues on the signal edge
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azonenberg>
i instead wait half a bit period
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smeding>
mine samples thrice
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smeding>
and does best of 3
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azonenberg>
Thats the alternate option
<
smeding>
i felt like overcomplicating
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azonenberg>
also, mine allows runtime changing of baud rate
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azonenberg>
though i usually synthesize it with a constant since i dont need to change it
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azonenberg>
and it optimizes out a few gates
<
smeding>
have to walk the dog
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azonenberg>
But theoretically as long as clkdiv does not change while a character is on the wire (in either direction) it should handle changing fine
<
smeding>
actually i had been for a while
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