<popolon>
need to translate text and comments but at least, there are bash commands
<rellla2>
morning
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<rellla>
tried to run xbmc with the new blobs and headers together with sunxi physical memory allocator driver but got ended up here: http://pastebin.com/eBuU1szc
<rellla>
any ideas where to start to search for what's missing?
<andoma>
are those supposed to fix the problems with weigted prediction in h264?
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<rellla>
andoma: most likely. but lets try them ourself. i tried them to work on A10. they are supposed to work at least on A20. proved by allwinner engineer, benn said.
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<focus>
popolon: well done! I hope to follow your blog and reproduce it soon
<focus>
popolon: ultimate aim is to create a gambas program to contain all these utilities as scripts and just run off each item by pressing buttons :)
<popolon>
yes :)
<popolon>
at least a short shell should be enough for some people
<popolon>
there is still a little problem with dhcp that doesn't make it work
<arokux2>
so aw is able of supporting that WiFi + BT4.0 + FM RX + GPS beast...
<oliv3r>
what beast?
<oliv3r>
that AP6something thing? where did you find it?
<atsampson>
the comment on the recent changes page translates as something like "fix performance problem with AP6476", so I googled for ap6476 datasheet...
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<wingrime>
oliv3r: CT wifi is opensource frendly?
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<oliv3r>
wingrime: no idea yet
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<arokux2>
any news from Benn in last days?
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<oliv3r>
he's on vacation
<arokux2>
good to know
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<oliv3r>
hey paul
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<arokux2>
mripard: hi, you there?
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<wickwire>
Hi guys, I'm having trouble getting ethernet working with a cubieboard 2 (A20) and following the sunxi First Steps wiki guide
<wickwire>
can anyone help?
<wickwire>
the sunxi-bsp worked,
<oliv3r>
wickwire: what kind of trouble; it should 'just work' :)
<wickwire>
I was able to produce a linaro SD card image and it booted fine
<wickwire>
but somehow, no ethernet device there
<wickwire>
on my other cubie (A10) it just works
<wickwire>
sunxi-bsp as well, same linaro rootfs
<mripard>
Turl: and you only tell me once it's merged ?
<wickwire>
I noticed that A10 cubie uses WEMAC
<mripard>
I said that I wanted to support the SoC, not the boards in the defconfig
<mripard>
but the modules are reasonnable to enable
<wickwire>
but on cubie2,
<mripard>
arokux2: yep
<wickwire>
I used ./configure cubieboard2
<wickwire>
then before make,
<wickwire>
I had to edit the chosen_board.mk and rectify the UBOOT entry
<wickwire>
from "cubieboard2" to "Cubieboard2"
<wickwire>
otherwise I would get a uboot generation error
<wickwire>
and the easy step with sunxi-bsp procedure worked
<wickwire>
I got a functional SD card image for the A20
<arokux2>
mripard: do you think "[linux-sunxi] [PATCH 1/4] reset: Add Allwinner A31 Reset Controller Driver" can be a general "single bit based" reset driver?
<wickwire>
but somehow, no ethernet
<arokux2>
mripard: at least it is needed for all of sunxi.
<wickwire>
if I choose to use Cubian's A20 image, I have ethernet
<wickwire>
unfortunately I had to destroy that one on my sd card to place the new linaro one
<wickwire>
so I don't have a means to compare
<mripard>
arokux2: it's already the case in the v2 I have pending for me to have some time to send it :)
<arokux2>
mripard: nice :) then I'm waiting for it and will read about phy framework now.
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<steev>
wickwire: add sunxi-emac to your /etc/modules or whatever that file is
<steev>
the module doesn't get auto loaded
<wickwire>
steev: I'll test it right away thanks
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<steev>
i'm not sure why it doesn't auto probe with the latest kernels, and i'm too busy to look into it
<wickwire>
steev: modprobe sunxi-emac won't work
<wickwire>
not found
<wickwire>
I'll have a look in the kernel sources I used
<wickwire>
from linux-sunxi git checkout
<wickwire>
and see where the option is
<wickwire>
I didn't mess with the kernel,
<steev>
sunxi_emac
<wickwire>
FATAL: Module sunxi_emac not found
<steev>
did you install the modules?
<oliv3r>
wickwire: wemac is a really realyl old driver; something smells that you are using old kernels :)
<steev>
that's definitely the module name, and it's in the sun7i_defconfig
<wickwire>
I followed the easy step in the guide
<wickwire>
sunxi-bsp
<wickwire>
./configure Cubieboard2
<steev>
wickwire: what does your /lib/modules/ look like
<wickwire>
make hwpack-install SD_CARD=/dev/sdX ROOTFS=your_rootfs.tar.gz
<wickwire>
lemme see
<wickwire>
/lib/modules/3.4.61/
<wickwire>
and then I have a sub-dir "kernel"
<wickwire>
and some files
<wickwire>
modules.alias, modules.dep,
<wickwire>
and "kernel" has...
<steev>
no drivers directory?
<steev>
kernel/drivers/net/ethernet/allwinner ?
<wickwire>
/lib/modules/3.4.61/kernel/drivers
<wickwire>
ahhh... nothing after /net
<steev>
steev@cubieboard2 /lib/modules/3.4.61+/kernel/drivers/net/ethernet/allwinner $ ls
<steev>
sunxi_emac.ko
<wickwire>
no /net/allwinner
<wickwire>
just /net/irda
<wickwire>
and /net/usb
<wickwire>
and some others
<steev>
i don't use the bsp, mostly because it was suggested to not be working when i was setting up my cb2
<steev>
and once i had gentoo installed *shrug*
<wickwire>
ahhh... ok
<wickwire>
anyways I'm checking the kernel inside the bsp
<wickwire>
and seeing if I have allwinner options
<steev>
check the .config
<wickwire>
maybe the bsp scripts didn't enable them...
<ss__>
I have developed a board that has 4 256mb ram chips
<ss__>
DDR3
<hno>
so a new untested board.
<ss__>
I am using DRAM parameters of Mele A1000G
<ss__>
Yes
<ss__>
untested
<hno>
du you have any other board to test your software on?
<mnemoc>
oliv3r: not sure where to upload them yet. but probably nightly/linux/
<ss__>
We has an evaluation board from WITS the allwinner support guys but it cannot boot from uSD
<hno>
the A10 EVB can boot from SD. You just need to find which SD slot is MMC0.
<oliv3r>
ss__: why A10? a10 isn't even sold anymroe is it
<hno>
s10 is still sold to those who ask for it.
<oliv3r>
ss__: have you tried hans'gs fedora image?
<ss__>
It is, we also have A20 but are starting with A10
<ss__>
If I change the uImage file to that in the linux-sunxi folder it goes further but stops at
<ss__>
<5>NFS: Registering the id_resolver key type
<oliv3r>
use one of hangs kernels
<hno>
I would guess it's either power of dram issues.
<oliv3r>
power could be it too yeah
<ss__>
I am using DC jack
<hno>
are you using an AXP?
<ss__>
I set the DRAM frequency to 360MHz
<wingrime>
oliv3r: I think PLL settings for a20 wrong for sata
<wingrime>
oliv3r: just guess
<wingrime>
oliv3r: but I think you should check it for a first
<oliv3r>
well wills wangs patch is very very similar to 3.3
<oliv3r>
and 3.4 (3.4 works too)
<oliv3r>
ss__: AXP is kinda important to keep power running smoothl
<hno>
ss__, what is the core & dram voltages when it hangs?
<ss__>
let me measure
<hno>
having the right voltages is important. AXP is just one tool for the job with full support in the AW sources.
<ss__>
core is 1.26V
<ss__>
DRAM is 1.51V
<ss__>
I also have 1.43V in one LDO that should be 1.2V
<ss__>
It was 1.2V previously
<Turl>
1.26 is a little low isn't it?
<hno>
that core voltage is a bit low. Should be around 1.4V at this stage before freqscaling kicks in and downclocks the CPU.
<ss__>
ok
<ss__>
Is there a setting I can change to fix it?
<Turl>
AW uses 1.25 for freqs lower to 624Mhz on their cpufreq driver
<Turl>
ss__: a setting where?
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<hno>
ss__, which AXP rail is your core voltage? And what is that LDO feeding?
<ss__>
just asking if it can be adjusted by a config file
<oliv3r>
what is your input voltage at that point
<ss__>
just to clarify the DCDC3 is 1.43V
<hno>
Odd.
<ss__>
but DCDC2 is 1.2V
<hno>
are you sure you have not mixed them up?
<hno>
power_failed |= axp209_set_dcdc2(1400);
<hno>
power_failed |= axp209_set_dcdc3(1250);
<ss__>
sorry
<hno>
is what u-boot sets them to.
<ss__>
It's DCDC2 1.43V and DCDC3 1.26V
<hno>
Ok, that is better.
<hno>
and DCDC2 is feeding the core power?
<ss__>
yes
<ss__>
for the CPU core
<hno>
so core voltage seems to be right.
<ss__>
ok
<hno>
around 1.4 V
<ss__>
Is it possible that my DRAM parameters need to be altered?
<hno>
possibly if your board is out of spec.
<ss__>
I'm using 360MHz
<ss__>
or my compiler?
<oliv3r>
a precompiled known to work kernel :)
<hno>
What frequency you can use depends on what chips you are using, how good your DDR3 dram wiring is, how good your ground planes are and some amount of luck in te design..
<ss__>
I am using version 4.7.1
<ss__>
What about the other parameter like CAS and ZQ, how do they affect
<ss__>
parameters
<oliv3r>
they depend on your ram parameters really
<oliv3r>
but they tend to be quite 'safe'
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<oliv3r>
have you tried a pre-compiled known to work kernel?
<oliv3r>
ideally a non-android kernel ;)
<ss__>
Yes
<ss__>
I tried a pengpod700 image
<oliv3r>
then something might be broken :(
<ss__>
it stops at
<ss__>
<6>hw perfevents: enabled with ARMv7 Cortex-A8 PMU driver, 5 counters available
<wingrime>
ss__: try 512 Gb
<ss__>
by broken you mean a non-functioning IC
<wingrime>
err
<wingrime>
Mb
<ss__>
H5TQ2G83CFR-H9C
<ss__>
is my RAM IC, I have 4
<ss__>
wingrime are you suggesting I use parameters for 512MB?
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<ss__>
I have tried that but it still hangs
<oliv3r>
you can always lower the density to 256mb to only use your first ram chip
<hno>
to only use on chip you would need to reduce bus width.
<hno>
not sure the A10 is happy with 8-bit bus widt.
* hno
needs to fix his h key.
<oliv3r>
i thought bus-wdith is always 8 or 16 bit
<hno>
A10 is 32-bit.
<ss__>
Currently I have set 2048 as the value for density
<hno>
io width is 8 or 16 depending on what chips you have.
<ss__>
I has set io width to 8
<hno>
which is correct for 4 x 8-bit chips.
<oliv3r>
i thought iow was for either 8bit or 16bit chips; and the bus width = iowidth * nr. of chips
<hno>
oliv3r, yes, 4 * 8 = 32
<oliv3r>
so what if you have 2x16bit?
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<hno>
2 x 16 = 32
<oliv3r>
erm 2x 8
<oliv3r>
:p
<hno>
have not seen that used on A10, only A13 which is 16-bit.
<hno>
ss__, you could try downclocking CPU and DRAM a lot an see if that helps.
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<ss__>
ok
<ss__>
Currently my processor is 1008MHz, how low can I go?
<wingrime>
60Mhz
<ss__>
ok
<wingrime>
hno: dram will still act on own speed
<wingrime>
hno: he can have problems with ddr3 routing where we can't help much\
<ss__>
The CPU speed can be lower that DRAM speed?
<wingrime>
ss__: es
<wingrime>
yes
<ss__>
ok
<wingrime>
ss__: but less pressure
<wingrime>
ss__: also, check how you soldered soc and ddr3
<Turl>
wingrime: 32khz work too
<wingrime>
ss__: any problems here fatal
<Turl>
but it's sloooooooow
<oliv3r>
wingrime: probably because of package; smaller package
<hno>
wingrime, what do you mean with dram will act on own speed?
<hno>
it's clocked by the DRAM controller.
<wingrime>
hno: yes
<wingrime>
hno: but not depend much from cpu
<hno>
Yes, that's obvious. The clocks are separate and only CPU clock can be easily tuned after start.
<oliv3r>
well on a10 you can't play with the mbus
<hno>
a10 do not have mbus.
<hno>
but mbus is internal to the DRAM & DMA controller.
<Turl>
what happened with mbus tuning after all?
<hno>
not sure. Been buried in bitcoin mining for the last months+
<wingrime>
hno: crazy stuff
<Turl>
hno: designing ASICs and the like?
<oliv3r>
no mbus or no tunable mbus on a10 ...
<oliv3r>
a13 does have mbus
<oliv3r>
(tuneable)
<hno>
Turl, yes, the company launched it's asic a week ago.
<Turl>
oliv3r: it's on sun5i and higher
<Turl>
hno: how long can you keep on selling those? I assume with the increasing bitcoin complexity there will be a point where ROI will be too long to be viable
<oliv3r>
the tuneabilty, but how can a1 not have an ambus at all
<hno>
Turl, correct.
<ss__>
I have reduced it to 450MHz, the result is still the same, I want to try 150MHz
<wingrime>
oliv3r: I think regs present
<hno>
wingrime, A10 do not seem to have mbus clock registers.
<oliv3r>
wingrime: they are but allways 0
<oliv3r>
i think it's a fixed mbu
<hno>
and the available diagrams and descriptions of a10 is slightly different in that area compared to the later designs.
<oliv3r>
AMBA i thought was the braodcom equiv. of ahb/axi/apb
<hno>
not at all.
<hno>
A in all of them is AMBA.
<hno>
and we have all of them in sunXi.
<oliv3r>
:D
<hno>
AXI is the highway with a mix of cars and huge trucks. AHB a road, APB s small bicycle lane.
<oliv3r>
nice anology
<oliv3r>
so where does the mbus fit here? Super speed highway parallel to the AMBA road-network?
<wingrime>
hno: cortex m have amba?
<hno>
Yes. amba is an umbrella of many things.
<wingrime>
hno: even on m0 or m1?
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<hno>
wingrime, yes. It's what is used for connecting the CPU core to anything...
<hno>
pretty much any design ARM7 or later uses AMBA, and is also frequently used in many other non-ARM SoCs as well to be able to reuse the same peripherial ecosystem.
<hno>
Re Cortex-M0 quote from ARM: "The Cortex-M0 processor implements a reduced version of the Advanced Microcontroller Bus Architecture (AMBA®), the AMBA-Lite bus"
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<hno>
wingrime^
<hno>
oliv3r, my gut feeling is that mbus is a specialised bus for display engine and some more which then connects to an AXI host port on the DRAM controller.
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<hno>
reducing some of the complexity of AXI.
<wingrime>
hno: on opencores there opensource AMBA replacment and arm compatible cpu
<hno>
yes. But most opencores componens are using wishbone instead of amba.
<hno>
another interconnect standard.
<mnemoc>
oliv3r: can you give me ARM: sunxi: sound-codec, add more controls + extend sun7i controls as a .patch ? patches with chinese don't work well on the ML + git am :(
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<mnemoc>
oliv3r: or a commit to cherry-pick?
<hno>
mnemoc, I did manage to massage one such patch into the right form with iconv earlier.
<mnemoc>
good hint
<hno>
think it got encoded as GB18030 but our repo is UTF-8
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