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<
libv >
hramrach: if there was one thing we at SuSE aimed for, then it was solid modesetting
11:27
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<
wingrime >
mripard: are there reset controller in a10?
13:41
<
wingrime >
mripard: can you add this in wiki
13:41
<
wingrime >
mripard: I want know about regs
13:41
<
wingrime >
mripard: also, I found old regs from sunII in sram contoller somone need check it
13:43
<
mripard >
it's in the user manual
13:43
<
wingrime >
mripard: a31 manual is not public
13:45
<
mripard >
you were talking about the A10
13:46
<
wingrime >
mripard: "Reset controller"
13:46
<
wingrime >
mripard: witch page
13:46
<
mripard >
they're part of the clock controller
13:47
<
wingrime >
mripard: not undocumented regs?
13:48
<
mripard >
look at what's called USB clock for example
13:48
<
mripard >
it's mostly a reset controller
14:05
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14:10
<
montjoie[home] >
anyone experienced with DMA know a good code example for using it ?
14:29
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14:35
<
Turl >
montjoie[home]: I'm pretty sure there is a test dma module in kernel
14:37
<
montjoie[home] >
ok thanks
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<
montjoie[home] >
I see all allwinner A1x DMA stuff declared in arch/arm/plat-sunxi/include/plat/dma_defs.h but only ofr SUN4I and SUN5I, is it normal that I see nothing for SUN7I ?
16:36
<
Turl >
montjoie[home]: I think hansg got DMA going on 3.4 for sun7i
16:36
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16:37
<
montjoie[home] >
ok, I could temporarly copy paste the same data
16:37
<
Turl >
montjoie[home]: check in arch/arm/mach-sun7i
16:37
<
Turl >
there is lots of dma stuff there too
16:38
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16:39
<
Turl >
montjoie[home]: there is a dma_compat.h header to support all sunx dma I think
16:39
<
Turl >
see for example commit 38cae4fb95bb
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<
montjoie[home] >
welcome to ifdef land
16:49
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16:59
<
wingrime >
Turl: if you have time, can you check undocumented sram regs
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<
Turl >
wingrime: link?
18:14
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<
oliv3r >
benn____: when is the CT expected to be shipped around the world?
18:56
<
Sonic1 >
mmm, Crazy Taxi
19:08
<
Turl >
oliv3r: eh, I thought they already did?
19:09
<
Turl >
oliv3r: I see it on r0ckstore
19:14
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19:15
<
wingrime >
Turl: our wiki
19:16
<
Turl >
wingrime: what page?
19:16
<
oliv3r >
ok when is it available for sale to the public
19:16
<
oliv3r >
not on backorder etc:)
19:16
<
oliv3r >
i thought only the developer models went out
19:18
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19:19
<
Turl >
oliv3r: it says it'll ship oct 14 on r0ckstore so I suppose it's selling already
19:20
<
wingrime >
Turl: I have added it from sunII so, they can be clearly same
19:20
<
wingrime >
Turl: but I think perfomance counters present
19:20
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19:20
<
Turl >
wingrime: user manual has sram reg
19:20
<
wingrime >
Turl: yes
19:20
<
wingrime >
Turl: but, not all
19:21
<
wingrime >
Turl: can you check that I added {unconfirmed}
19:22
<
Turl >
wingrime: how can I check?
19:22
<
wingrime >
Turl: devmem.c / uboot / reg read sunxi driver
19:23
<
wingrime >
Turl: in case counters you can just play with regs and write to sram
19:23
<
wingrime >
for see whats changed
19:23
<
wingrime >
Turl: but more interested thing, it have BIST, build in self test
19:25
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19:27
<
wingrime >
Turl: yes, but you have play with bit fields
19:27
<
wingrime >
Turl: for find somethig
19:28
<
wingrime >
Turl: SRAM_AC320_P_EN
19:29
<
wingrime >
Turl: thats must enable performance counter
19:29
<
wingrime >
oliv3r: ping
19:29
<
oliv3r >
wingrime: poing
19:29
<
wingrime >
oliv3r: can you add all to 1 for A10 in SRAM page
19:30
<
Turl >
wingrime: see page 100 A20 user manual
19:30
<
Turl >
wingrime: 0x30 NMI
19:31
<
wingrime >
Turl: a20 can be different
19:31
<
wingrime >
Turl: it have GIC
19:31
<
Turl >
wingrime: reusing addr is odd
19:32
<
Turl >
wingrime: usually they add after last item
19:32
<
wingrime >
Turl: I have added if from sunII
19:32
<
wingrime >
Turl: they defenetly reuse
19:33
<
wingrime >
Turl: so, I think
19:33
<
wingrime >
Turl: thats counters still there
19:33
<
wingrime >
Turl: but offset can be changed
19:34
<
wingrime >
Turl: for example 0x54 and 0x58 for a31 defenetly some flag
19:34
<
oliv3r >
erh, i can try, but have my cb1 at worka tm
19:35
<
wingrime >
oliv3r: that add a20
19:35
<
wingrime >
oliv3r: 0 and all to 1
19:37
<
wingrime >
oliv3r: how you using cb at work?
19:38
<
oliv3r >
hacking :p
19:38
<
oliv3r >
not for $work; just @ $work
19:39
<
wingrime >
oliv3r: )
19:40
<
wingrime >
oliv3r: can you check a31 man
19:41
<
wingrime >
oliv3r: are 0x54 and 0x58 documented for SRAM controller
19:43
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19:46
<
wingrime >
oliv3r: ?
19:46
<
oliv3r >
i'm kinda updating my system; 223/613 packages upgraded :)
19:49
<
wingrime >
benn____: ping
19:53
<
oliv3r >
wingrime: 0x0 sram control 0; 0x04 sram control reg 1; GPU DXT BC Enable reg 0x50; GPU SW Clock gating reg 0x54; GPU IDLE status reg 0x58; GPU Power status reg 0x60;
19:55
<
oliv3r >
wingrime: those are mostly powerVR registers in the sram area; but nothign is documented about the other register
19:55
<
wingrime >
oliv3r: thats good
19:55
<
wingrime >
oliv3r: we need A20 0 and all to 1
20:05
<
wingrime >
oliv3r: cool, if it can have dcache/icache read counters
20:10
<
oliv3r >
i think they are hidden registers though :(
20:11
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20:11
<
wingrime >
oliv3r: but counters for sunxii cedar was correct
20:12
<
oliv3r >
i bet they will still be; so they can be very usefull
20:12
<
oliv3r >
(if you know what they do ;)
20:15
<
wingrime >
oliv3r: ok, I will dump a20
20:30
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20:33
<
wingrime >
oliv3r: thats strange
20:33
<
wingrime >
oliv3r: some times I was able tun to 1 some bit
20:33
<
wingrime >
but other times not
20:34
<
wingrime >
hno: ping
20:35
<
wingrime >
hno: uboot use caches ?
20:35
<
wingrime >
hno: cpu cache enabled?
20:37
<
wingrime >
oliv3r: 00008000: dffb4b41 dffb4b41 dffb4b41 dffb4b41 AK..AK..AK..AK..
20:38
<
wingrime >
after I writed 0xffffffff
20:38
<
wingrime >
are you sure that works
20:38
<
wingrime >
A3 sram section
20:38
<
oliv3r >
wingrime: make sure you do 32bit aligned writes
20:38
<
oliv3r >
yeah sometimes you aren't allowed to write everywhere
20:39
<
oliv3r >
sometimes it depends on various clocks etc
20:39
<
wingrime >
oliv3r: but same time A2 works
20:40
<
wingrime >
oliv3r: but you claimed thats workable
20:40
<
wingrime >
oliv3r: I mean somehow A2 "read only"
20:41
<
wingrime >
oliv3r: after my play
20:41
<
oliv3r >
writing all 1's can be confusing
20:41
<
wingrime >
oliv3r: not all
20:42
<
wingrime >
oliv3r: only 0x30-0x40
20:42
<
wingrime >
oliv3r: I have some theory
20:42
<
wingrime >
oliv3r: i will check
20:44
<
wingrime >
oliv3r: thats a20
20:44
<
wingrime >
oliv3r: I have that after boot
20:45
<
wingrime >
oliv3r: yeax thats RO
20:45
<
oliv3r >
that looks interesting!
20:45
<
wingrime >
read only
20:48
<
wingrime >
oliv3r: A4 also RO
20:50
<
wingrime >
Turl: ping
20:50
<
wingrime >
Turl: have any idea why A3 and A4 SRAM not works with a20?
20:52
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20:52
<
Turl >
wingrime: A3 A4 emac
20:53
<
Turl >
wingrime: "SRAM_A3_A4_MAP"
20:54
<
wingrime >
Turl: a20 have differnet default set for sram_ctr1
20:54
<
wingrime >
Turl: A10 have 0x1300, A20 have 0x1314
20:55
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20:56
<
wingrime >
oliv3r: wtf
20:56
<
Turl >
wingrime: A20 map A3-A4 to EMAC then according to A10 User Manual
20:56
<
wingrime >
oliv3r: 4 means 3 bit
20:58
<
wingrime >
err 2, if count from zero
20:58
<
wingrime >
but its undocumented
20:59
<
Turl >
wingrime: 0x10 makes it map to emac on a20 and 0x00 to cpu on a10
21:00
<
wingrime >
Turl: what to emac, witch sram part
21:00
<
Turl >
wingrime: A3-A4
21:00
<
wingrime >
Turl: we have 4:5 for this
21:00
<
Turl >
wingrime: yea
21:00
<
wingrime >
Turl: but thats 2
21:00
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21:00
<
Turl >
wingrime: 0x10 is bit 4
21:00
<
wingrime >
Turl: thats means something to EMAC
21:02
<
Turl >
wingrime: if you write 0x1304 to register it should be rw
21:03
<
wingrime >
Turl: I will try
21:04
<
wingrime >
Turl: you right
21:10
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21:21
<
hno >
wingrime, yes u-boot enables some caches. And flushes them carefully when handing off to the kernel.
21:28
<
wingrime >
hno: thanks
21:31
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21:33
<
oliv3r >
Turl: i documented that on the wiki even iirc
21:38
<
wingrime >
oliv3r: I ind some intersting things
21:38
<
wingrime >
oliv3r: 0x14 register
21:39
<
wingrime >
oliv3r: its auto incrementing
21:39
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21:39
<
wingrime >
oliv3r: every time you write his lower part
21:46
<
oliv3r >
DWORD, that word makes my bones shiver
21:47
<
oliv3r >
i was referring to that with the emac thing
21:48
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21:49
<
wingrime >
Turl: can you play with 0x14
21:49
<
wingrime >
Turl: thats behave very strange
21:49
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21:50
<
wingrime >
Turl: that reg have readonly part and write
21:50
<
wingrime >
Turl: first two bytes contol something
21:50
<
wingrime >
Turl: for example writing 40 to it will produce r/o part cahnge some bits
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wingrime >
err looks
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wingrime >
writing 0x40 change nuber in hi part
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wingrime >
writing 0x0 change it back
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aexl1 >
hi. what's the actual brightness (cd/m²) of the flying squirrel lcd?
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libv >
aexl1: #arm-netbook
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aexl1 >
duh. sorry.^^
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