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<kronicd>
I know this isn't likely the place to ask, but I have no idea where the right place is. I have an allwinner tablet, I have nand backups of all the /dev/block/nand* devs, and I have a non-stock phoenixsuite image which works perfectly (android) aside from GPS, which is completely disabled.
<kronicd>
Is there some way to enable GPS? :(
<wens>
is there a GPS module on board?
<kronicd>
Yeah, the stock firmware had it work without issue, sirfstar III
<wens>
there's multiple things involved, like enabling the uart, having the gps module powered up, and registering it with the system?
<wens>
don't know how android handles gps
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<kronicd>
understood, I guess more from the allwinner chip perspective, it seems there is more to the configuration than the /dev/block/nand* contents itself
<MoeIcenowy>
wens: maybe there's something in allwinner sdk document
<wens>
fex file might have a gps related section
<kronicd>
I've extracted the configuration from the pheonixsuite image that works and have the ctp_para, gps_para etc
<kronicd>
it does
<kronicd>
Is there a way to figure out the correct settings from the nand dumps I have?
<kronicd>
actually if the ko file contains the firmware/whatever I'll also try just moving those from the nand to the other device as well
<kronicd>
nand image*
<wens>
you could try that, though kernel modules are typically bound to the image they were compiled with
<wens>
you might get random crashes
<kronicd>
ok, well just coping them over the top didnt change anything at all
<kronicd>
hrm
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<kronicd>
well without use of the touch input I managed to install and launch a GPS app
<kronicd>
so now I can see if its worth pursuing :P
<kronicd>
annnd confirmed
<kronicd>
I have one image with broken GPS, one image with broken touchscreen, and a set of stock nand images
<kronicd>
at least across them I do have a set of fully working things!
<Zliba>
what's the #armbian channel?
<Zliba>
how does one verify the integrity of armbian images? there's no checksum or pgp sig
<kronicd>
confirmed its not GPS_PARA
<kronicd>
unpacked the working one, nothing int here either
<kronicd>
there must be something else, touch stuff still broken in the same way
<kronicd>
ctp_para changed, firmware changed
<kronicd>
exactly the same issue
<kronicd>
Ive managed to find a bunch of GPS settings which are messed up though
<kronicd>
so might swap back to attempting to fix gps
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<kronicd>
lBaudRate="921600"
<kronicd>
I think that might have been part of the problem
<kronicd>
what the hell is that
<kronicd>
weirdest thing is, even when I dd all the nand images back into place
<kronicd>
the display issue remains
<kronicd>
or when I replace all the gps files/configs
<kronicd>
I think I have a fundamental misunderstanding of how this stuff works
<kronicd>
WORKS!
<kronicd>
replaced module, replaced configs,
<kronicd>
:D
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<lennyraposo>
more from AllWinner
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<plaes>
lennyraposo: more what?
<lennyraposo>
just reading through it
<lennyraposo>
sorry
<lennyraposo>
Here is Allwinner response:
<lennyraposo>
I means when using gcc complie xorg, the funwind-tables doesn't enable and this cause the xorg_backtrace()->stack return back value 1, then only can trace up to stack point first layer and appear /usr/bin/X (xorg_backtrace+0x5c) [0x55909ca75c]. If need to trace more layer of stack pointer, enable funwind-tbles is needed. Reload backtrace() stack still facing similar issue and currently only able to figure
<lennyraposo>
issues with funwind-tables on compile is what I gather from it
<kronicd>
you wot m8
<kronicd>
so trying to parse that sort of language while dealing with allwinner stuff is pretty standard?
<lennyraposo>
From the 0x7f7875600c address reference to proc/pidof(X)/maps. I don't think we are yet in video library, and thsi is why need to trace down next stack pointer relationship.
<lennyraposo>
We don't have experience on compiling xorg, and may facing more issue and longer the development cycle.
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<lennyraposo>
this has ot do with eir work on a 64bit Mali 400 driver
<lennyraposo>
kronicd
<lennyraposo>
my understanding of AllWinner interaction is that it can be difficult
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<lennyraposo>
from teh sounds of things they need xorg to be compiled for their dev puproses
<lennyraposo>
also wondering what toolchain they are using
<lennyraposo>
which begs the question
<lennyraposo>
what toolchain are they using
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<lennyraposo>
gota night of compiling ahead of me
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<kasper>
hello
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<KotCzarny>
now someone should pm that user to provide citations and references of opensourcerness
<KotCzarny>
(and revert the change if its not true)
<tkaiser>
Nora Lee is Banana Pi PM at Foxconn. But I fear she lacks any understanding (especially about 'open source'). She also produces countless fake videos on youtube showing Banana Pi features that do not work (HW accelerated video decoding / GPU acceleration)
<KotCzarny>
tkaiser, but she can forward mails to someone responsible
<KotCzarny>
and warn her that bpi page might get locked
<tkaiser>
(I asked for hardware descriptions and they get back with the question where .dts might be -- WTF?)
<NiteHawk>
I'm just asking becaus that sentence seems a bit biased and we might just as well do without it?
<NiteHawk>
The incompatibility warning is fine by itself, i think.
<tkaiser>
NiteHawk: Yeah, I'm fine with removing it (also on other SinoVoip pages) since they learned some lessons and eventually released even Lamobo R1 schematics after a year or so
<tkaiser>
NiteHawk: A year ago it looked differently. Regarding BPi M2 they really didn't provide anything. But given the hardware is really just a Xunlong rip-off now that makes some sense. But issues with newer boards are more or less resolved.
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<NiteHawk>
We all know that support quality from these companies tends to be lousy - they deserve some bashing. But we should to to keep some balance / neutrality on the wiki, and try to stick with the facts (which are often simple/telling enough). I've toned down the wiki page a bit
<NiteHawk>
will check the other sinovoip's too (m2/m2+)
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<tkaiser>
NiteHawk: Thx
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<ssvb>
kasper: which kernel are you using?
<kasper>
ssvb: 3.4.109-sun7i
<kasper>
ssvb: sunxi_wdt driver builtin
<ssvb>
kasper: maybe this is the problem, because a10-stdin-watchdog uses the watchdog from userspace via mmio
<ssvb>
kasper: if your kernel driver is kicking the watchdog periodically, then the board will not reboot
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<ssvb>
NiteHawk: thanks for reminding, I'll have a look later today
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<enrico_>
bbrezillon: back with nand questions :D i have u-boot and rootfs working from nand (olinuxino micro and lime2, kernel 4.6, u-boot chip next), but i noticed that the bbt is re-initialized at every boot: http://pastebin.com/BJumc5Qz
<enrico_>
it happens only on the micro boards, not on lime2. apart from some software error that i could have made, what is causing it to be re-done every time?
<enrico_>
(tried nand scrub from u-boot etc... of course)
<kasper>
enrico_: what version of uboot do you use to boot from nand?
<enrico_>
a chip version plus some patches to enable it on my boards, i can tell the exact one if you want
<kasper>
enrico_ is this better choice than allwinner nand uboot 2011?
<enrico_>
kasper: never tried that ancient thing :D
<kasper>
hm.. i tried, because i didnt know that other nand boot version exist
<enrico_>
well they are not "ready to go", apart from chip maybe
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<kasper>
ok, what chip do you use?
<kasper>
a ok micro, lime2 sorry
<kasper>
enrico_ what tool do you use to build and burn firmware?
<bbrezillon>
enrico_: I don't know
<bbrezillon>
I've seen that when Linux and u-boot do not use the same BBT flags (like one is setting _BBT_NO_OOB and the other one is not)
<bbrezillon>
at each boot u-boot fails to detect a valid BBT, erase the last 2 blocks an write a new one
<bbrezillon>
and Linux does the same
<bbrezillon>
have you tried to dump this block?
<enrico_>
kasper: manually (yocto, nandwrite and friends)
<kasper>
ok thanks
<enrico_>
bbrezillon: no, is it possibile that they are two bad blocks?
<bbrezillon>
according to the scan they are not bad
<enrico_>
it's strange that i don't see that on lime2 (two boards actually), while i use same kernel and u-boot (compiled with different config of course)
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<enrico_>
bbrezillon: i was wondering, if i scrub the nand (so i delete "real" bad blocks), how they will be detected again as bad blocks?
<enrico_>
during flash_erase? ubiformat?
<bbrezillon>
well, they might not be marked as bad again
<bbrezillon>
but from my experience, most of those blocks cannot be erased and you get an error from the chip when it fails
<bbrezillon>
so they're still considered as bad even after scrubbing the NAND
<enrico_>
bbrezillon: ok, thanks (i think i have seen something like that during my tests)
<bbrezillon>
this being said, this strategy is not entirely safe
<bbrezillon>
some of them might be erased even if they are really bad, and in this case you'll see data corruption at some point
<enrico_>
but at least when you try to read a bad block you should get an error (ecc or whatever), so it could be detected in some way
<bbrezillon>
well, yes etheir when programming it, or when reading it back
<enrico_>
for example i think ubiformat verify your flashed image, so at least it's something
<bbrezillon>
yep
<bbrezillon>
but some of them are considered bad because they do not retain data over-time
<enrico_>
but if a block is moved away for wear levelling, and it lands in a bad block (not marked as such)?
<enrico_>
perfect hehe
<bbrezillon>
so this is not something you'll be able to verify with a simple read
<enrico_>
uhm it happened that a board that i'm sure was booting from nand stopped working from one day to another
<enrico_>
maybe it's that
<bbrezillon>
anyway, I'm almost sure livesuit does not retain those BBM anyway, so when we get a NAND that has already been programmed by livesuit we probably already lost this information
<bbrezillon>
enrico_: with Allwinner's implementation or the MTD/NAND one?
<enrico_>
no my latest setup
<enrico_>
chip u-boot etc
<enrico_>
mtd/nand one
<bbrezillon>
with UBI/UBIFS?
<bbrezillon>
which part started to fail?
<enrico_>
yes, u-boot didn't attach/mount it anymore
<enrico_>
spl and u-boot always loaded, ubifs (for rootfs) stopped to be recognized from u-boot
<enrico_>
booting from an sd-card, then trying to attach ubi from linux i got tons of ecc errors
<bbrezillon>
we have 2 different problems with MLC NANDs, the first one is interrupting a program operation (power-cut), might not only corrupt the page you were writting, but also another page you already programmed
<bbrezillon>
and UBI/UBIFS are not expecting that
<bbrezillon>
the other problem is that, on some NANDs, when you partially write an eraseblock, you got tons of bitflips in some pages, and at some points those bitflips turn into uncorrectable errors (because of read-disturb)
<bbrezillon>
so, until we come with a reliable solution to deal with that in UBI, the only way to have a reliable solution is to use the NAND in SLC mode, which divides the NAND storage capacity by 2
<enrico_>
that would be ok for me :D
<bbrezillon>
well, there's a generic solution to support that, but it's not yet been submitted (or even developed)
<bbrezillon>
what we use for the CHIP is the hardware SLC mode provide by the Hynix NAND
<bbrezillon>
but since this is a private per-vendor/chip feature, I'm sure sure it will be supported on your chip
<bbrezillon>
my generic solution would instead use the pairing scheme information to implement a 'software SLC mode'
<bbrezillon>
I'll try to provide an implementation. What's your NAND chip again?
<bbrezillon>
enrico_: ^
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<enrico_>
bbrezillon: from the datasheet it seems that for slc you "just" need a different addressing (one bit less in page addresses), i think it's the software slc mode you were referring to, using pairing information
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<bbrezillon>
enrico_: well, not exactly, you still need to switch the NAND in SLC mode
<bbrezillon>
maybe it's the same command though
<bbrezillon>
and the addressing is definitely different
<enrico_>
on that datasheet it only refers to slc in addressing mode, unfortunately no commands
<enrico_>
well since the address contains the plane address, in theory you just need to keep it at a fixed value
<enrico_>
" The Address consists of column address (A0~A13), page address (A14 ~ A21), plane address (A22),and block address (A23 ~ the last address)."
<enrico_>
ugly hack, i know :D
<bbrezillon>
you'll have to right shift the page value
<enrico_>
infact for slc it says: " The Address consists of column address (A0~A13), page address (A14 ~ A20), plane address (A21),and block address (A22 ~ the last address)."
<enrico_>
one less bit in page address
<bbrezillon>
try that and keep the ->set_slc_mode() implementation used for the H27Q
<bbrezillon>
well, that's not exactly a right shift :-/
<enrico_>
but since it is exposed as 4GB, who will "tell" the system that it's really 2 GB now?
<bbrezillon>
it's already handled in the UBI layer
<bbrezillon>
I think I had an implementation for that one, let me check
<enrico_>
at this point i think it will be easier to split the nand in 2 partitions and make a raid1 :D