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<perfstr_>
I am trying to create my own USB gadget based on sunxi_usb_udc and GadgetFS. I can't find any details about sunxi_usb_udc and after successful startup detection I am unable to get data sent by host side. How can I proceed?.
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<perfstr>
How can I see older messages from today?
<Amit_T>
montjoie: Hello, wanted to know what extra changes are required to make external PHY work(Enable RMII Module bit needed to set , apart from it)
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<montjoie>
Amit_T: Setting syscon is the only thing to do
<Amit_T>
ok
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<Amit_T>
montjoie: I tried it on A64 but it didn't work, is this cache invalidation api's same for both armv7 and armv8 ?
<montjoie>
I think
<montjoie>
my driver is the same for a64 and h3/a83t
<Amit_T>
ok
<montjoie>
the only call added for 64bit is the dma mask
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<Amit_T>
and where you do it ?
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<tuxillo>
morning
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<montjoie>
Amit_T: see my v2 branch, dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
<Amit_T>
ok, Thanks.
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<BlueberryPie>
have you ever heard of the NEC OPS-DRD? It uses A31 but i can't get it working with debian...
<BlueberryPie>
rip
<BlueberryPie>
porcoddio
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<ssvb>
apritzel: btw, did you manage to successfully use flashrom on your pine64 in the end?
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<apritzel>
no, not really
<apritzel>
I did use that spidev tools from the kernel tree
<apritzel>
and that worked, I could read the SPI flash ID registers, for instance
<MoeIcenowy>
why are you now caring about SPI Flash boot?
<apritzel>
but flashrom didn't recognise the chip for some reason
<MoeIcenowy>
I don't think the vendors who uses Allwinner SoCs will want to pay for one more flash chip
<apritzel>
though I didn't really debug it, so it could be well a stupid error on my side
<ssvb>
MoeIcenowy: why not? it's a nice option for the boards which have neither NAND not eMMC
<apritzel>
MoeIcenowy: SPI flash boot solves some issues for instance with UEFI
<apritzel>
also you can always put it on the headers
<ssvb>
apritzel: according to the recent posts in the linux-sunxi mailing list, the current sunxi SPI driver is a little bit dodgy and does not support messages longer than the FIFO size
<apritzel>
I plan to solder some plug-like device with a 5x2 pin header plug, which you just put on the RPi2 header and are good to go
<apritzel>
ssvb: ah, that could explain it
<apritzel>
maybe one could hack flashrom to use a smaller message size for the time being
<ssvb>
it may have some other problems too, I guess the biggest issue is that this driver has no real users and was poorly tested
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<Wizzup_>
ssvb: likely I'll be able to try the spi flash on the a10/a20 tonight
<ssvb>
Wizzup_: thanks!
<MoeIcenowy>
apritzel: In fact I want also to have UEFI running on sunxi platform :-)
<MoeIcenowy>
but what did I think is to run a UEFI as U-Boot payload
<apritzel>
MoeIcenowy: well, upstream U-Boot already support a fair bit of it: you can run a EFI grub2 from U-Boot, for instance
<apritzel>
also I think agraf booted an EFI Linux kernel directly from U-Boot already
<wens>
wow
<TheLinuxBug>
ssvb: I will likely try and order an SPI this week sometime and some new solder and will give it a test too if I can get the time here
<wens>
apritzel: fyi amlogic s905 will use SCPI as well
<wens>
patches submitted for the kernel by baylibre
<apritzel>
wens: really? awesome ...
<wens>
the patchset doesn't really say how it's implemented though
<apritzel>
wens: anyway, found it, thanks for the heads up!
<apritzel>
and since Sudeep's desk is two metres from mine ... ;-)
<apritzel>
would anyone object against an A64 specific mainline kernel task list in the Pine64 (or A64) wiki page?
<apritzel>
I see that this overlaps with the mainlining effort page, but I wonder if spilling A64 specific stuff in there is more annoying than it helps
<apritzel>
also I want to dump hints and explanations there
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<wens>
apritzel: you could always list things on the mainlining page in the WiP section, under an "A64" item
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<MoeIcenowy>
apritzel: uboot bootefi seems to be only usable on aarch64
<MoeIcenowy>
but not arm32
<apritzel>
MoeIcenowy: sure about that? I think agraf enabled both?
<apritzel>
not that anyone cares about 4-bytes-at-once anymore :-p
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<agraf>
MoeIcenowy: it should work on both
<agraf>
MoeIcenowy: doesn't it work for you?
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<MoeIcenowy>
agraf: on my machine arm32 have no bootefi
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<agraf>
MoeIcenowy: are you running 2016.05?
<MoeIcenowy>
agraf: oh no
<MoeIcenowy>
i'm on 03
<MoeIcenowy>
thx
<agraf>
too old then :)
<MoeIcenowy>
2016.03 is too old?
<agraf>
for bootefi, yes
<agraf>
it only got into 2016.06
<agraf>
eh 05
<MoeIcenowy>
(and can bootefi now boot a sunxi kernel with efistub?
<agraf>
I haven't tried yet, in theory it should :)
<agraf>
armv7 efi stub support is pretty new itself
<MoeIcenowy>
and... can I run an a10 cubieboard u-boot on qemu?
<agraf>
I haven't been working on armv7 for a few months now - it's been all aarch64 :)
<MoeIcenowy>
:-) I also want an aarch64 board
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<MoeIcenowy>
but I'm too poor now
<agraf>
MoeIcenowy: rpi3? :)
<agraf>
MoeIcenowy: pine64?
<agraf>
MoeIcenowy: there are plentty cheap options now
<agraf>
MoeIcenowy: also I don't know if the a10 emulation in qemu is good enoguh to run u-boot
<MoeIcenowy>
pine64 will take too much time for shipping
<MoeIcenowy>
and I didn't find the 64-bit kernel file for rpi3
<ssvb>
MoeIcenowy: maybe TL Lim can provide a pine64 board to you for free, you could ask
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<MoeIcenowy>
qemu still cannot load u-boot-dtb.img
<ssvb>
MoeIcenowy: at least you seem to be skilled enough to do something useful with it, so everyone wins :)
<MoeIcenowy>
I'm only a distro developer
<ssvb>
MoeIcenowy: haven't you submitted some kernel patches recently?
<MoeIcenowy>
ssvb: yes, but they're only small fixes
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<MoeIcenowy>
(qemu cannot be used to debug u-boot on sunxi...
<MoeIcenowy>
(maybe we should develop a free replacement of BROM for qemu
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<jelle>
agraf: rpi3 can't use 64 bit yet
<jelle>
MoeIcenowy: the orange pi guys should hurry up with their 64 bit :p
<lvrp16>
MoeIcenowy: what boards do you need?
<lvrp16>
jelle: we are launching an a72 based computer, hopefully by end of this year/beginning of next year
<MoeIcenowy>
a72 based? not allwinner?
<ssvb>
marvell?
<jelle>
lvrp16: who is we? :-)
<lvrp16>
not allwinner
<lvrp16>
me and some friends ;)
<MoeIcenowy>
so what soc
<lvrp16>
rk3399
<MoeIcenowy>
rk...
<lvrp16>
we should have prototype boards by september
<MoeIcenowy>
Are the ones who submit the rk3399 drivers rk stuff?
<lvrp16>
20k production run around december/january
<MoeIcenowy>
(At least I haven't seen AW stuff to submit mainline patches
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<lennyraposo>
lvrp
<lennyraposo>
sounds interesting
<lennyraposo>
got a price point for the boards?
<lennyraposo>
lvrp16*
<lennyraposo>
sorry ;)
<maz>
lvrp16: hopefully you'll route the PCIe lines to proper connectors? because that's what is really interesting about the rk3399.
<lennyraposo>
yep
<lennyraposo>
aslong as everything is not tied into usb this should be quite the performer
<lennyraposo>
:D
<lennyraposo>
lvrp16 let me know when you got things on the go with your venture
<maz>
lennyraposo: well, that and memory.
<lennyraposo>
very true
<mnr>
Are there publicly available SoC manuals for the various RockChip SoCs?
<ssvb>
mnr: generally, it is probably a good idea to check websites of rockchip devboard manufacturers to see if they have something to offer, because it is in their best interests
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<ssvb>
mnr: for example, we have a very similar situation with Allwinner A64 and have all the technical reference manuals from board manufacturers too (Pine64 and OLIMEX), while the official Allwinner website only offers marketing bullshit
<Wizzup_>
ssvb: don't have a winbond yet, but looking at MX25L6406E
<Wizzup_>
(which I have here right now)
<ssvb>
Wizzup_: I have just checked the manual, it should be fully compatible
<ssvb>
Wizzup_: so just connect the wires and it should work
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<Wizzup_>
ssvb: yeah, just need to figure out if I connect MOSI to SIO1?
<Wizzup_>
SI/SIO0 *
<Wizzup_>
and MISO to SO/SIO1 I guess
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<apritzel>
ssvb: the BPi-M1 doesn't work with SPI boot, right? Because the BROM configures the C port, and the BPi headers use the I port?
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<apritzel>
Wizzup_: M stands for master, S for slave, the board is the master, the flash is the slave: that pretty much tells it
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<Wizzup_>
apritzel: yeah, I was mostly figuring out if SI/SIO0 was basically what the wiki refers to as "DI", but that seems like it
<apritzel>
yes, DI = data in on a slave is MOSI
<Wizzup_>
Now I need to figure out why my olimex UEXT seems to invert all the pins (1 is 2, 2 is 1), etc
<apritzel>
depends on whether you look from the top or the bottom?
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<Wizzup_>
the pins are numbered on UEXT too
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<Wizzup_>
> No. The LIME2 design swaps the signals of each row of each 0.5" step header. All four GPIO headers and the LCD header are affected. Shields made for LIME boards can't be connected directly to a LIME2 board.
<Wizzup_>
That ... would explain it
<ssvb>
Wizzup_: I got temporarily disconnected, but apritzel already explained everything
<ssvb>
Wizzup_: UEXT? How is it related?
<ssvb>
Wizzup_: You have soldered wires to the PC0, PC1, PC2 pins on the NAND socket, right?
<ssvb>
Wizzup_: the PC23 pin is chip select, and it should be pulled up by the SoC by default
<Wizzup_>
ssvb: I wanted to connect the 3v3,gnd and spi0 cs
<Wizzup_>
those are on the gpio1 header on the lime
<Wizzup_>
together with the PC0,PC1,PC2 I should be set
<ssvb>
Wizzup_: right
<Wizzup_>
but it seems that the LIME and LIME2 have the gpio pins swapped
<Wizzup_>
no biggie, just one more invertion;-)
<Wizzup_>
(so my LIME UEXT with LIME2 requires me to swap)
<ssvb>
Wizzup_: hmm, this is extremely weird, why would they do this?
<Wizzup_>
ssvb: what I described above, where pc0 and pc2 seem to have contact (multimeter confirmed), only happens when I lime on the lime(hold the fel button), and then only after issuing ./sunxi-fel -v spiflash-info
<ssvb>
Wizzup_: maybe that's fine too, reading is also not happening all the time and there are pauses in SPI transfer when the chunks of data are sent over USB
<Wizzup_>
I probably have better measurement tools here, but I'm don't feel confident using them yet (can ask someone for help tomorrow)
<ssvb>
Wizzup_: if you can measure some voltage change at all, then the CS pin is likely controlled correctly
<ssvb>
do you get 3.3V on the CS pin after the transfer is done and there is no SPI activity anymore?
<Wizzup_>
I get 3v when transfer is done
<Wizzup_>
2.35 hwhen during transfer
<ssvb>
ok, then it is most likely fine
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<Wizzup_>
I double checked the miso/mosi solder work and it seems fine
<Wizzup_>
so either both these chips are bad, or something else is up
<Wizzup_>
just double checking - I connected MOSI/PC0 to SI/SIO0
<Wizzup_>
and MISO/PC1 to SO/SIO1
<ssvb>
you get MOSI, MISO and CS pins apparently operating correctly at least from the SoC side
<Wizzup_>
I wanted to verify that I didn't swap MISO and MISO
<Wizzup_>
(p.s. for my tests wrt cs voltage I reverted the info test patch)
<Wizzup_>
although I don't believe that matters
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<ssvb>
yes, the test patch should not make any difference
<ssvb>
a silly question, have you also provided 3.3V power to the SPI chip? also are you sure that you got pins numbering right?
<Wizzup_>
it seems to be powered. but I'm going to reconnect the 640.
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<ssvb>
Wizzup_: you can also try to experiment with the SPI phase and polarity in the SPI_CTL register (bits 2 and 3)
<Wizzup_>
ssvb: I think I got the power connections right, yeah
<Wizzup_>
I connected the 3v3 pin on the lime to the vcc pin of the flash chip
<Wizzup_>
and the gnd to gnd...
<ssvb>
that's correct
<Wizzup_>
ssvb: can you elaborate on that a bit? where in the code would that be done? grep'd for SPI_CTL but didn't find anything
<ssvb>
Wizzup_: and also check the A20 manual for the SPI_CTL register bits
<Wizzup_>
ok
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<Wizzup_>
I'm probably going to wrap up for today though, close to 0:00 AM and I need to bike home
<ssvb>
Wizzup_: I assumed that the reset defaults for the CPHA/CPOL bits should be already reasonable, but maybe we need to change them to be compatible with your chip
<Wizzup_>
Thank you for your help, much appreciated
<Wizzup_>
I'm hoping to get a winbond chips real soon
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<ssvb>
Wizzup_: ok, see you later
<Wizzup_>
That may be an easier test case?
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<ssvb>
it's best to check the SPI chip manual (they may have some recommendations) and then configure the same setup
<ssvb>
we definitely want to have other SPI flash chips supported too, not just Winbond