<apritzel>
budovi: and add labels to the CPU node above, so that it reads: cpu0: cpu@0 { ....
<apritzel>
(for the other CPUs respectively, of course)
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<budovi>
apritzel: it worked, thank you again
<apritzel>
budovi: good to know! do you use perf on it? Are the numbers reasonable?
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<budovi>
yeah plan to use perf, I used it before but wanted some cache counters that are not available without PMU support
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<budovi>
so spoke too soon apparently.... counters seem to work (perf stat) but perf is not woken up on the events (perf record) thus I cannot observe which parts of code are responsible
<budovi>
maybe those PMU IRQ settings in the device tree are not correct / compatible with the rest.. not sure
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<apritzel>
budovi: yeah, looks like an IRQ problem then
<apritzel>
tbh I didn't test this myself, and the report was apparently just for the counters
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<apritzel>
mmh, just checked the manual again, at least the numbers seem to match here (152+ => 120 + 32)
<apritzel>
budovi: have you compiled a matching perf?
<apritzel>
perf seems to be very picky about the kernel it talks to, also is quite often broken on arm/arm64
<Amit_T>
apritzel: Actually I tested this on pine64 and share the output here, must be IRC logs
<Amit_T>
must be *in IRC logs
<apritzel>
Amit_T: but did you test just "perf stat" or also "perf record"?
<budovi>
I'm using Arch Linux and perf is installed from repositories right now...
<apritzel>
Amit_T: yeah, that's just the counters
<Amit_T>
budovi: Can you share your output ?
<apritzel>
budovi: do you mind trying to compile perf from the very same source tree you compiled the kernel from?
<apritzel>
I know that perf is a PITA in this respect (because it lives in the kernel source tree and thus can afford to have a very close relationship)
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<budovi>
will try to build my perf then... Amit_T: what output are you interested in?
<budovi>
apritzel: they are present there during perf execution, listed as GICv2 152-155, type Level... and there are zeroes
<budovi>
so no, not a single interrupt is "delivered"
<budovi>
sounds like pmu is not configured properly...
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<apritzel>
budovi: but the PMU is pretty architectural (part of the A53 core)
<apritzel>
budovi: that smells like we just got the wrong interrupt numbers
<apritzel>
so the PMU driver enables those IRQs, but they never trigger
<budovi>
well either allwinner's manual is wrong or they're correct...
<apritzel>
and those that fire stay disabled
<apritzel>
I wonder if someone with a H3 board could confirm this (PMU operation with perf record works and triggers IRQs)
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<maldata>
Still on the Merrii Hummingbird H2 here... does anyone know how to check which version of u-boot is currently installed?
<jelle>
maldata: should show up on boot
<maldata>
jelle: including whether it's mainline u-boot or sunxi u-boot? Or can I only determine that based on the version number?
<jelle>
not sure if that can be determined, I've only used mainline u-boot
<maldata>
jelle: thanks. Any gotchas that I should be aware of if I upgrade to the latest mainline u-boot (from either an older mainline or from sunxi)?
<maldata>
I pretty much just plan on doing a normal u-boot install right over the existing one.
<jelle>
well is it supported?
<jelle>
maldata: and which kernel you use, since again I only used the mainline kernel ;-)
<maldata>
As far as I know, yes. It's an older board.
<maldata>
it's the sunxi 3.4 kernel, currently
<jelle>
maldata: no experience regarding that also it doens't have an entry on the sunxi wiki
<maldata>
jelle: thanks for the input! I'm going to just have to give it a try. I've got the whole sd card imaged out to my host PC, so things can't get too horrible.
<jelle>
maldata: I can't see support in mainline for it btw
<jelle>
so I wouldn't try it
<maldata>
jelle: in mainline u-boot?
<jelle>
maldata: I think yeah
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<maldata>
jelle: u-boot lives on the sd card, right?
<montjoie>
just updated my emac V4 branch, next step is to send it
<tkaiser>
montjoie: Is there anything worth to test?
<montjoie>
the only real change is the adding of the patch you tested
<montjoie>
the remaining is respelling of patchs
<montjoie>
but this time I will send all patch (including those needing regulator)
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<apritzel>
tkaiser: aren't the EMAC and GMAC already listed separately for the A20?
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<tkaiser>
apritzel: Don't know. Have to admit that I never looked into A20 specs since I came too late (all the hard work already done by this wonderful community here)
<apritzel>
tkaiser: to me the R40 looks the same as the A20 in this respect: separate MMIO frames, separate IRQs, EMAC has two different pin sets, GMAC has only one (muxed with one EMAC)
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<apritzel>
tkaiser: so it should be already possible to use two distinct Ethernet interfaces on the A20
<apritzel>
unless there is something either I miss or the documentation doesn't tell
<tkaiser>
apritzel: Well, it would require a hardware vendor trying to build a device and able to ask Allwinner, right?
<apritzel>
I guess so
<apritzel>
or a board vendor brave enough to just give it a try
<apritzel>
but then again apparently Allwinner may not support this in their software drops, so board vendors don't even think about it ;-)
<tkaiser>
apritzel: true
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<apritzel>
if this EMAC is compatible to the one from the A10, then support for this scenario in upstream Linux would be a matter of 5 minutes DT editing
* apritzel
hopes that someone listens ;-)
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<tkaiser>
apritzel: Are you interested in getting the M2 Ultra? I guess they would send one to you if you ask
<KotCzarny>
spewing new chips so often while community isnt completely mainlined even first ones
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<nove>
A, B, F, G, H, R, T, V, VR
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<nove>
B and G have in soc wiki
<nove>
B of Book reader, maybe?
<nove>
in soc wifi*
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<montjoie>
apritzel for R40 i see sun4i-ss to be incompatible
<KotCzarny>
it might be close to h3?
<montjoie>
I think/hope
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<apritzel>
the R40 seems like an A20 with some parts from the H3 (MMC comes to mind)
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