Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> MoeIcenowy: afaik there's a framework for loading firmware into coprocessors in the kernel
<wens> maybe it wasn't merged
<kilobyte> for any kind of firmware, or even arbitrary blobs of data
<kilobyte> the userspace must be up at that time, though
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<kilobyte> actually, looks like it's possible to read it directly from a fixed place on the filesystem (which might be an initrd)
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<swiftgeek> i hope somebody will document how to do it :>
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<itdaniher> anyone have experiences they'd like to share wrt A64 close-to-mainline kernels? expecting my pinebook shortly, will be my first A64 machine.
<itdaniher> probably my first 64b ARM running anything besides ios or android
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<tllim> @itdaniher, check with BenG83, he has teh Pinebook mainline build that contribute by Icenowy.
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<tkaiser> Can someone with upload access to dl.linux-sunxi.org please put http://kaiser-edv.de/tmp/lGtv38/patch-add-support-xr819.tar.gz there and update the link on http://linux-sunxi.org/Wifi#Allwinner ?
<Ke> development with tarballs and patches again in fashion =o)
<tkaiser> Ke: Well, latest Allwinner code drop for XR819 ('latest' == Sep 2016)
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<swiftgeek> is H3 cpufreq capable ?
<KotCzarny> yes, when someone write proper driver
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<swiftgeek> then nice red NO would be great there ;P
<KotCzarny> nah, it's just someone added row and updated it only for 2 boards :P
<jelle> swiftgeek: well nothing == no right ;-)
<jelle> also it's a wiki, you can fix it
<KotCzarny> you can add green yes for a20
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<KotCzarny> while you are at it
<swiftgeek> 4.0 i presume
<KotCzarny> dont know when it was added, so either investigate or just write 'OK'
<jelle> 4.0 it is
<jelle> KotCzarny: it's mentioned on the page and huh also mentions 'all SOCs'
<KotCzarny> and NO is used when there is no driver in bsp and no one plans to write it
* jelle is confsued by that
<KotCzarny> well, scratch the bsp part
<KotCzarny> red: ' No support, nobody works on it '
<KotCzarny> btw. isnt THS related to cpufreq a bit?
<KotCzarny> ahm, dvfs is more like it
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<mripard_> not really
<KotCzarny> does cpufreq grab operating points automatically from dvfs?
<mripard_> THS is just reporting the temperature of the SoC
<mripard_> if using THS, you see that it gets too hot, then you can set constraints on the frequency used by cpufreq in order to cool down a bit
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<mripard_> but cpufreq can operate fine without THS
<swiftgeek> KotCzarny: updated
<mripard_> and THS can operate fine without cpufreq
<swiftgeek> cpufreq row ;P
<KotCzarny> my guess is that 'all socs' update could mean something like that
<MoeIcenowy> wens: remoteproc?
<MoeIcenowy> mriprad_: when will you merge the H3 PLL_CPUX fix patch?
<wens> MoeIcenowy: yeah, I think that was it
<mripard_> MoeIcenowy: when the rework will be done
<mripard_> there's no rush, really
<MoeIcenowy> ok ;-)
<MoeIcenowy> maybe I should now first prepare a dvfs table for h3 ;-)
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<plaes> mripard: o/
<plaes> I think A13 devicetree will need some updates for simplefb nodes
<plaes> <&ccu HDMI> for hdmi path
<mripard> plaes: hmmm, A13 doesn't have HDMI :)
<plaes> hmm.. :D
<plaes> ok, TVE has its own clock too?
<mripard> yes
<plaes> I don't have HW for that
<plaes> anyway, ccu will turn of unused clocks, including TVE then
<plaes> s/of/off
<plaes> at least this is what happened with HDMI simplefb output on A10/A20
<plaes> anyway, I think I have now addressed most of your comments on the sun4i ccu
<plaes> although, SATA is somewhat unsorted yet
<wens> i think i commented on the SATA clock some time ago?
<wens> what's the remaining issue?
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<plaes> actually, there are two SATA related issues in this letter
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<wens> plaes: first, pll-periph-sata should be a gate + divider + fixed post divider
<wens> so just like the old clock driver, you need pll-periph-base, which is 24M * N * K
<wens> pll-periph-base = pll-periph-base / M / 6
<wens> oops, meant pll-periph-sata = pll-periph-base / M / 6
<wens> pll-periph = pll-periph-base / 2
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<wens> then sata = mux( pll-periph-sata , sata-ext ) + gate
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<plaes> k, thanks :)
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<diego_r> Hi guys, is there a software way, better if from Linux, to tell which revision of a board I'm running? I'm particularly interested in Olinuxino A20 Lime2
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<KotCzarny> nope, unless you find yourself what features are different between revisions and probe/compare them yourself
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<diego_r> KotCzarny: understood. no magic fuse bit or stuff like that so...
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<orn> Hi, first post here. Does anyone here have experience with bluetooth drivers for rtl8723bs? I'm trying backports now.
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<wens> MoeIcenowy: ^
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<KotCzarny> hmm, what does PSCI field in status matrix mean? relying on uboot setting it or something else?
<wens> U-boot provides PSCI support
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<plaes> diego_r: you might want to try #olimex
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<diego_r> plaes: thanks for the hint
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<lvrp16> damn shenzhen and it's mosquitos, eating me alive
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<rpd_> clear
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<rpd_> hi, I have run into the dreaded network issue with Pine64 board, but don't understand it fully, is it a hardware issue or something I can correct by using the right build/os?
<lvrp16> 2GB?
<rpd_> yeah
<MoeIcenowy> what issue?
<MoeIcenowy> link is up but cannot transmit data
<MoeIcenowy> ?
<lvrp16> A64 + 2GB + Ethernet, i thought that problem was resolved long ago?
<MoeIcenowy> not on mainline.
<rpd_> it seems to drop packets, initially the connection starts fine, then degrades until it stalls
<rpd_> I was able to boot "pine64-image-debianbase-310102bsp-2.img", but it is not booting latest armbian release for pine64, considering it boots the other, I am guessing its not a sdcard/power issue, so am a bit clueless as to what to do
<MoeIcenowy> what's the kernel version?
<rpd_> I think it is 3.10.102-BSP-2
<MoeIcenowy> 3.10.102... seems a bit old BSP variant
<MoeIcenowy> for BSP problems please go #Pine64 on irc.pine64.xyz
<MoeIcenowy> not here
<rpd_> ok thanks, can you recommend a more recent image I can try
<MoeIcenowy> I don't know...
<rpd_> if I build my own using dbootstrap on a vm would that be one way to go?
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<IgorPec> sorry, i saw you are having troubles ... strange
<rpd_> IgorPec: thanks, I am actually trying to work through your suggestions online, I downloaded Debian_jessie_default.7z, but my board is not booting that image...
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<IgorPec> ok. sorry, don't have pine64 to checkup. better ask / check on forum.armbian.com
<rpd_> IgorPec: yes let me try other images like Ubuntu and see how it goes, trying to stick to debian due to as wanted to integrate into a dev cluster, lets see...
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<IgorPec> let's move our chat to #armbian since this channel is not covering this topic
<rpd_> ok will do thanks!
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<BenG83> MoeIcenowy, did you have any luck reproducing GbE issues
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<wens> oh wow, rtl8723bs in staging
<BenG83> oh wow
<MoeIcenowy> BenG83: yes
<MoeIcenowy> with the board from my friend
<BenG83> because I have seven boards now from different batches and they all work with GbE regardless of kernel version
<BenG83> I have yet to find one that doesnt work
<KotCzarny> beng83: try with weak psu maybe?
<MoeIcenowy> KotCzarny: it's not a PSU problem.
<KotCzarny> i remember someone mentioning that rmi wasnt powered enough with weak psu
<rpd_> BenG83: reporting success with ubuntu image from longsleep, specifically https://www.stdin.xyz/downloads/people/longsleep/pine64-images/ubuntu/xenial-pine64-bspkernel-20161218-1.img.xz
<rpd_> 30 MB in 10/sec for apt-get upgrade
<rpd_> so seems like a software issue
<rpd_> with old kernels, will try latest armbian now
<MoeIcenowy> in fact it's a hardware issue
<MoeIcenowy> but it's workarounded in newer software
<rpd_> MoeIcenowy: interesting, would like to read more about it...
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<longsleep> rpd_: https://github.com/longsleep/linux-pine64/commit/ffe3ca5be7682bbeb0fdadede29acd4a3c888015 - there is not much more information about those flags
<wens> montjoie: sun8i-dwmac 1c30000.ethernet: Current syscon value is not the default 148000 (expect 58000)
<wens> sun8i-dwmac 1c30000.ethernet: EMAC reset timeout
<rpd_> longsleep: thanks, interesting stuff..., I notice that the yellow led blinks a lot more erratically than the green one, which is odd compared to rest of the sbc boards I have
<IgorPec> we use the same kernel
<IgorPec> sorry
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<BenG83> longsleep, afaik it does the same as pulling down the RXDLY pin which is usually only power-on configurable
<BenG83> 28
<BenG83> RGMII Receiver Clock Timing Control.
<BenG83> 1: Add 2ns delay to RXC for RXD latching
<BenG83> O/LI/PD
<BenG83> RXDLY
<BenG83> e.g. disabling that 2ns fixed delay
<BenG83> which offsets the registers tuning range
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<wens> montjoie: why do you call sun8i_dwmac_reset() in sun8i_power_phy()?
<wens> and sun8i_dwmac_reset should be sun8i_dwmac_dma_reset
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<rpd_> see you folks again!
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<orn> exit
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<tillzz> Hi there, is someone here who knows a bit about the SPI drivers for sun8i SoCs? I'm experiencing a strange problem with the Linux Mainline Driver (which doesn't appear in sunxi-linux), and i'd like to find out the reason to be able to fix it.
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<TheLinuxBug> tillzz: they answer is probably yes, there is someone, however, you will need to hang out and wait a while if you want a reply, people here are in a wide variety of time zones and may not see your request for a while.
<tillzz> @TheLinuxBug yeah, didn't expect sth different ;-)
<TheLinuxBug> Just making sure you were aware and didn't just /quit in 5 minutes ;p
<TheLinuxBug> can't tell you number of times that happens and someone answers the question like 10 minutes later
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<MoeIcenowy> tillzz: which sun8i?
<tillzz> H3
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<MoeIcenowy> what's your slave?
<MoeIcenowy> Currently (4.11 and former) spi-sun6i cannot do transfers larger than chip's FIFO
<tillzz> As far is i can see, the mainline driver is just the sun6i with a few patches. My Slave is an AVR µC which I want to program
<MoeIcenowy> what patches?
<MoeIcenowy> I think for spi-sun6i to support larger transfers two patches are needed
<tillzz> yes, know that… But that's not the problem… I observed the whole bus, and there's a really short pulse one the SCK line before the `real` SCK clock starts
<MoeIcenowy> oh really strange...
<tillzz> http://lxr.free-electrons.com/source/drivers/spi/spi-sun6i.c#L28 (that's what i saw what is sun8i related)
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<tillzz> yeah, this won't be a problem in most use cases, as the CS is still high at this pulse, but the AVR's synchronize their clock to the length of the first pulse… and as this is simply so short, they're switching to 'failure' mode
<montjoie> wens: you got that on which board?
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<montjoie> wens: the first message is just a warning, uboot certainly leave emac enabled
<montjoie> wens: the sun8i_dwmac_reset is needed for let MAC seee the syscon value change
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<dgp> tillzz: if you don't need performance bitbang spi on the same pins could work for now
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<tillzz> yeah, doing that at the moment without problems, but my goal is not 'just getting it to work' ;-) Especially when i add more slaves to the bus, that's going to be a really hacky solution, to switch between native-spi & bitbang.
<wens> montjoie: h3 orange pi pc
<wens> montjoie: then that warning is kind of useless :p
<wens> montjoie: syscon value change?
<wens> found a few more cleanups
<wens> like you don't need to check if the pointer is valid for clk_* and reset_control_* calls
<wens> they ignore NULL pointers
<wens> and you don't need to take stmmaceth clock, it's done by the driver library
<dgp> tillzz: how fast is the clock. You could fix it with some 74 series logic too :D
<dgp> I don't remember seeing weird clock pulses like that when messing around with the spi controller to make a crappy uboot driver for it
<tillzz> 3000Hz, slowest possible (but tried many different speeds)
<montjoie> wens: strange my opipc work
<tillzz> dgp damn… where can i find the code of that driver? Already compared differences between mainline and sunxi, proably a minimal driver would help ;-)
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<tillzz> (If you're interested: thats how it looks: http://pasteboard.co/6e8uMdxpo.bmp )
<montjoie> wens: will fix NULL checks
<wens> argh, right, i disconnected my cable and connected to a usb dongle
<wens> silly me
<wens> will test tomorrow once i connect a separate cable
<MoeIcenowy> yes my boards seem to also fail
<wens> montjoie: also, it's custom to have register bit field macros use the register name as its prefix
<dgp> tillzz: I remember having my logic analyzer wired up to check what it was doing and not seeing anything weird on the clock
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<wens> montjoie: what values from syscon does it pick up? or needs to pick up?
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<montjoie> wens: syscon values are generated from the default but i think i didnt understand well your question
<wens> montjoie: why do you need the reset just after syscon is programmed
<wens> you shouldn't need it
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<montjoie> if i didnt reset after syscon, the phy change is ignored
<montjoie> it is with that that I foound that the internal PHY was an AC200 and it accept gigabit
<wens> huh?
<wens> i don't follow
<wens> MII PHYs can't do gigabit
<montjoie> I have removed this reset in the past on Bpim2+, and strangely I got very bad perf in gigabit
<montjoie> the reason was that all was done with the internal PHY
<montjoie> link managed at gigabit
<montjoie> but AC200 cannot
<montjoie> go below 150Mbit/s
<wens> that sounds fishy in any case
<montjoie> so for me, the syscon reg is read at reset
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<ssvb> somebody has observed something similar, but just disappeared after receiving some advises and never reported back
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<swiftgeek> do i see correctly that 8189FTV has no blobs?
<tillzz> ssvb: Thanks, no, didn't see it - I searched explicit for the H3, but of course it's likely to appear on other SoCs too. I'll then play a bit with the driver…
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<KotCzarny> swiftgeek: on android there is some fw file, but is it used..
<KotCzarny> who knows what is it for
<BenG83> o/
<swiftgeek> KotCzarny: perhaps update? it's hard to tell without any datasheet :<
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<KotCzarny> no, its a tiny file
<swiftgeek> then regdomain/calibration for sure
<swiftgeek> or ROM patch :P
<swiftgeek> btw what's the jwrdegoede nick here?
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<MoeIcenowy> swiftgeek: there is blobs
<MoeIcenowy> but they are in char* array form in some .h file
<swiftgeek> i don't quite see it
<swiftgeek> except that code is terrible :P
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<MoeIcenowy> See hal/phydm/rtl8188e/halhwimg8188e_*
<swiftgeek> oh rtw_security.c
<MoeIcenowy> the big arrays
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<swiftgeek> now i know where all the space went ;/
<swiftgeek> halhwimg8188e_s_fw.c
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<swiftgeek> but it still looks a bit strange
<swiftgeek> i guess i could try slashing it
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<KotCzarny> urm. i'm either going crazy or my opipc's sid changed
<KotCzarny> might be that i've calculated it wrong before too.
<MoeIcenowy> P.S. check the serial in /proc/cpuinfo
<MoeIcenowy> it will keep the first word of SID readout
<MoeIcenowy> if
<KotCzarny> i'm doing it via sunxi-tools
<MoeIcenowy> if it used to be 02004620, then that is wrong
<KotCzarny> for now
<MoeIcenowy> if it's started at 02c00081 thus it's correct
<KotCzarny> should i also get ram markings?
<MoeIcenowy> I think currently no needed ;-)
<MoeIcenowy> but the CPU marking is valuable
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<KotCzarny> hrm, serial in cpuinfo is 10 bytes long
<KotCzarny> and weird
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<KotCzarny> oh, it's ok. serial in cpuinfo (legacy kernel) consists of bytes 8-11 and 16-31
<KotCzarny> i've updated all 3 h3 boards entries
<KotCzarny> one of my opipc is almost identical with nitehawk's
<KotCzarny> might be sa,e batch
<KotCzarny> *same
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<KotCzarny> MoeIcenowy: did you notice tat v3 and r40 have similar first 4 bytes?
<KotCzarny> *that
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