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<MoeIcenowy>
mripard: now I think the display muxes are so complex on R40...
<MoeIcenowy>
there's a mux that takes two DE2 mixers as input and takes 4 TCONs as output
<MoeIcenowy>
there's a mux that takes two TCON_TVs as input and output to the HDMI controller
<MoeIcenowy>
and there's two clock muxes (for TCON_TVx, select between CCU TCON_TVx clocks and clock output of TVEx) and three clock gates (for two TCON_TVs and DSI)
<MoeIcenowy>
this part is called TCON_TOP in user manual
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<oliv3r>
Net147: i'm just going over your sun4i_hdmi_i2c driver work (been using it works fine) but I notice something off in your data: #define SUN4I_HDMI_I2C_LINE_CTRL_REG0x40
<oliv3r>
(that is 0x540 btw) but there's nothing at that address in the A20 datasheet. The data is at 0x524 however. I'm not sure if we are using this register at all (i think you can use it to reset the I2C line manually if it got stuck)
<oliv3r>
(without involving the pinctrl)
<wens>
it's undocumented (again)
<plaes>
btw.. I have a small hdmi display and A20 never manages to read ddc data in u-boot
<oliv3r>
wens: where is the documentation for it? as 0x524 and 0x540 seem to do slightly different things
<oliv3r>
plaes: i think we never set the pinmux for PI20 and PI21, which afaik luckly does default to i2c for hdmi
<plaes>
hmm.. nice hint
<plaes>
I'll check it when home
<oliv3r>
so on power-up it _should_ be fine
<oliv3r>
ah 0x540 seems to be the DDC_DBG register
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<oliv3r>
ahah, the A31 hdmi controller is quite different
<wens>
it is
<oliv3r>
i actually mean the hdmi-ddc controller
<wens>
the A20 has separate pins for HDMI SCL/SDA
<oliv3r>
but i'm sure hdmi is different as well
<oliv3r>
and the A31? how does that one do it?
<wens>
you should not need to mux pins if the board layout uses them
<wens>
for the A31, separate pins as well
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<oliv3r>
wens: what do you mean, not mux the pins? I was talking about the i2c pins of the hdmi, you can actually check the status (like a gpio) and toggle it (like a gpio) while in I2C mode.
<oliv3r>
this is extremly usefull, to reset a 'stuck' I2C bus (which can happen with mis-behaving devices)
<KotCzarny>
ooh, how do you reset i2c bus ?
<oliv3r>
by 'taking over controll' of the bus and manually toggle the lines
<wens>
oliv3r: you mentioned pinmux above, I'm saying you don't need to
<KotCzarny>
could you write some tool to do it?
<oliv3r>
wens: as far as I can tell, the default mux on those pins is HDMI-i2c; so you don't need to mux them theoretically. OTH its never a bad idea to explicitly set them to said mux, if you are using the pins as i2c
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<oliv3r>
KotCzarny: i would let the kernel do it imo, 'if bus keeps timing out, reset bus'
<oliv3r>
KotCzarny: i'm not sure if there's an ioctl but i think there was talks a while ago about it
<oliv3r>
KotCzarny: i know some drivers actually have hacked that in too, re-mux the pins to gpio, do the thing, mux them back to i2c
<wens>
oliv3r: doesn't look like it (default mux to HDMI-i2c)
<oliv3r>
KotCzarny: but in our case, we don't have to as we have the DDC_EXTENDED_CTRL_REG
<oliv3r>
wens: did I overlook it in u-boot?
<KotCzarny>
i have a problem that sometimes i2c/ddc doesnt work on boot (putting hdmi to sleep and waking fixes it, but would like to do it in some easier way)
<oliv3r>
wens: the kernel doesn't (yet) i'm working on a patch to actually do that explicitly
<KotCzarny>
(i'm using h3)
<wens>
oliv3r: why would you have it mux default to i2c?
<oliv3r>
KotCzarny: well toggling the i2c lines only helps when a remote device is confused (like it received only 7 out of 8 clock pulses)
<oliv3r>
wens: because I did not see u-boot setting it up properly, so it was my assumption only :)
<oliv3r>
wens: as for the kernel, if you use hdmi-i2c, we should have the pinctrler mux it. right now i think it relies on u-boot to mux it properly or the default is set to i2c
<wens>
oliv3r: and nor does u-boot
<oliv3r>
KotCzarny: and you need to manually clock out the remaining clocks
<wens>
what did I just say? hdmi i2c has separate dedicated pins
<oliv3r>
wens: so the default for PI20/PI21 seems to be hdmi-i2c then
<oliv3r>
because if that's not it, i'm confused as to what PI20 and PI21 are
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<oliv3r>
as I did find it somewhere explicitly mentioned the H being HDMI, which made me go 'ohh'
<oliv3r>
that sucks
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<wens>
you seriously need to get your facts straight
<plaes>
:D
<oliv3r>
wait, let me find where it is 'documented'
<wens>
the LIME, like all other A20 boards, route HDMI DDC to pins R22, R23 on the SoC, which are HDMI-SCL and HDMI-SDA
<wens>
these are dedicated pins, like the other HDMI pins
<oliv3r>
i'll double check where i found the reference
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<oliv3r>
so what is HSDA and HSCL
<oliv3r>
and what is function: hdmi, groups = [ PI20 PI21 ]
<wens>
probably an alternative route
<oliv3r>
i've pulle dthat stragiht from grep hdmi pinmux-functions
<plaes>
hmm..totally different mux on A10/A20
<wens>
those are possibly mux functions, yes
<plaes>
A20 mux = 4, A10 mux = 6
<plaes>
according to wiki :P
<oliv3r>
so if they come out on R22 and R23, what happens if i set the mux on PI20 and PI21, R22 and R23 get disconnected?
<oliv3r>
plaes: i bet that's a typo on the wiki
<oliv3r>
plaes: but who knows :)
<oliv3r>
wens: so my facts weren't that off!
<wens>
oliv3r: you're free to experiment
<plaes>
yeah, so which one is right?
<oliv3r>
if those are indeed additional muxes
<oliv3r>
wens: obviously i will :p
<oliv3r>
as we are using uart7 right now
<wens>
point being no boards actually use that function
<oliv3r>
wens: that we know off :p
<oliv3r>
but i'd agree
<oliv3r>
i woner though what the point is of having the mux, if there's dedicated pins
<wens>
oliv3r: stop trying to use the hdmi-ddc controller in creative ways
<oliv3r>
wens: i can't
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<wens>
I'm guessing the undocumented bits in 0x540 enable whatever buffer between the hdmi ddc block and the dedicated ddc pins
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<oliv3r>
the only thing I have found so far is 'DDC_DBG', but it's nowhere documented. The thing that triggered me is net147's driver, where he is doing something to the register and calls it 'line ctrl reg'
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<wens>
which was likely found in the old 3.4 kernel, and in u-boot
<wens>
but why are you digging through drivers anyway?
<oliv3r>
i'm cleaning it up a bit :)
<wens>
please don't just yet
<wens>
I'd have to rebase my A31 driver yet again :/
<oliv3r>
wens: why? maxime has merged it into his for next
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<oliv3r>
wens: a31 ddc driver?
<wens>
a31 hdmi driver, including ddc
<oliv3r>
is yours based ontop of maxime's latest for-drm-4.14 stuff?
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<wens>
yes
<oliv3r>
wens: link me; then i'll rebase uppon yours
<oliv3r>
wens: would that work for you?
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<oliv3r>
your github a31-hdmi work is from quite a while ago :(
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<oliv3r>
wens: you are right, the 3.4 ksunxi_disp_regs says 540 is the line_ctrl and calls the actuall line_ctrl 'unknown_0'
<wens>
I've not worked on it during this cycle, was mainly focused on a83t and reviewing patches
<oliv3r>
if you could push whatever you have onto your gh (or point me which repo i should pull) i'll go from there
<wens>
oliv3r: my a31-hdmi-v2 branch doesn't look so old?
<oliv3r>
a31-hdmi-v2 Updated a year ago by wens
<oliv3r>
looked old to me :p
<oliv3r>
but that's gh maybe being an ass
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<oliv3r>
then i'll rebase ontop of that
<wens>
hah, git commit --amend doesn't reset the date by default, so you're seeing when I first started that uncompleted driver
<oliv3r>
annoying :S bug-report :)
<oliv3r>
yeah that v2 looks very up to date
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<oliv3r>
hmm, that 3.4 code seems to have been 'named' by us, so could be wrong still
<oliv3r>
(even though it is mostly commented code) we change from writing into register 0x505 (strange addr) to 0x540 (which really is the debug register)
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<oliv3r>
though the 3 << 8 'enable analog sda/scl pad' still puzzles me, (which are bit 8 and 9 in the current code)
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<oliv3r>
either the debug register abused, or they wrongfully write into the 'status' bits
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<oliv3r>
time to debug that and see what happens :)
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<oliv3r>
an 0x505 somehow got translated instead of 506 .. (unless 504 + 1 = 506
<oliv3r>
Net147: have you ever verified those bits?
<oliv3r>
maybe the 540 analog 'pad' enables/disables those muxes ...
<Net147>
oliv3r: I think that part was in mripard's original code
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<Net147>
oliv3r: I only changed the DDC command from explicit to implicit and the transfer algorithm
<oliv3r>
Net147: ah, then mripard took the code probably from suni 3.4
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<MoeIcenowy>
wens: what muxes did DE1 SoCs have?
<MoeIcenowy>
(I mostly cared DE2 now, and the only DE1 SoC that I had experience is A33, which is quite simple
<wens>
MoeIcenowy: mux between de-fe and de-be, mux between de-be and tcon, mux between tcon and hdmi/tve
<wens>
it's roughly the same
<MoeIcenowy>
but in DE2 there's no mux between fe and be ;-)
<MoeIcenowy>
(and... I think we currently doesn't care FE at all!
<KotCzarny>
does is only for singular third person
<KotCzarny>
:)
<MoeIcenowy>
thx
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<oliv3r>
ok so bit8 and bit9 deffinatly seem to enable output, and thus i would not be supprised if that's basically the r22 pin controller
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<oliv3r>
just have to PI20 and PI21 in the pinmux to double check the behaviour there
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<wens>
MoeIcenowy: so? the bits between the engine, tcon, and encoders are still similar?
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<MoeIcenowy>
wens: yes...
<MoeIcenowy>
but in DE2 the mux is standalone, not in the components
<MoeIcenowy>
for H3, H5, A64 mux is in CCU
<MoeIcenowy>
for R40, H6 mux is in TCON_TOP
<wens>
so the only issue is either mapping the registers, or using a syscon
<wens>
or some other device and adding some API
<montjoie>
pfff my emac mux series goes big, finding too many bugs
<MoeIcenowy>
in fact I wonder why ALL dwmac-sun8i DT bits are reverted?
<MoeIcenowy>
I think we only have problem on H3/H5
<MoeIcenowy>
wens: I think we may abstract them...
<MoeIcenowy>
in the DT
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<KotCzarny>
btw. upped new h3ii
<KotCzarny>
oops, wrong chan
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<oliv3r>
alright, for our collective knowledge pool; it seems that the ddc extended register is more or less the pinctrl of the hdmi-i2c block. you can toggle the bits as a gpio via this register, but it has no influence on the other muxed output.
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<oliv3r>
and so it appears that the debug register indeed is also a 'pinctrl' register
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<buZz>
mg
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<gnufan>
I'm using since some time and it's quite effective. of course when the I2C bus is so "fu£$ed up", the problem is adifferent one, but at least this workaround try to "recover" something.. hope it helps!
<wens>
the DT is not the place for abstraction
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<ElBarto>
plaes: mripard: clkng for A10/A20 will be for 4.14 or 4.15 ?
<wens>
4.15
<ElBarto>
thanks :)
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<gnufan>
umh, sorry, it looks like my IRC client can't deliver properly my posts so i see on "irclog" the msg of mine looks pretty clueless.. :-)
<KotCzarny>
yup
<gnufan>
let me repost..
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<gnufan>
oliv3r: hi, i see your issue about HDMI-DDC I2C recovery technique, let me contribute with my experience on A20 generic I2C module..
<gnufan>
the LINE CTRL register is there too.. ad offset 0x20 IIRC
<gnufan>
and as i had some issues with a noisy bus i resorted to use it, enhancing the mv64xxx generic i2c driver that mainline sunxi is using..
<gnufan>
after a quick survey of a number of I2C kernel drivers, it's clear that it'a a common practice for ruggedized modules.. so SW bindings are already in place..
<gnufan>
i didn't published it because it would take some time to make it a "quirk" option of the standard I2C mv64xxx kernel driver.. who knows which SOC is using that cell.. i don't know if the others do have this extra LINE CTRL reg..
<gnufan>
so feel free to get inspiration about it.. IIRC the A20 user manual shows pretty well on a picture that this "out of band" control of the I2C lines is "hijacking" the wires without interfering with the "state machine" of the I2C HW module..
<gnufan>
and, finally, I'm using for some time and it's quite effective. of course when the I2C bus is so "fu£$ed up", the problem is adifferent one, but at least this workaround try to "recover" something.. hope it helps!
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<python476>
hi there
<python476>
I was looking for current/watt figure about different allwinner SoC