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<martinayotte>
@MoeIcenowy, you didn'tn answered me : But I can still see "sun4i-usb-phy 1c19400.phy: failed to get clock usb0_phy". Should we care ? Should we remove usb0_phy from A64 ?
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<MoeIcenowy>
martinayoutte: I think it doesn't matter
<wens>
if it works in the end, it's probably just the deferred probe
<wens>
if it doesn't work, then we have a problem
<MoeIcenowy>
wens: have you seen my reply on the R40 clk patchset? (at Jul 210
<MoeIcenowy>
s/210/21)/
<MoeIcenowy>
P.S. why does the A64 pll-periph{0,1}'s K has a min value of 2?
<MoeIcenowy>
from the user manual it says The range is from 1 to 4
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<MoeIcenowy>
oh I think for implementing pll-periph0-sata on R40 I will need "clk: sunxi-ng: div: Add support for fixed post-divider" from plaes
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<wens>
MoeIcenowy: just replied, sorry
<wens>
I keep thinking I've missed a bunch of patches
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<rajkosto>
it works with the module i compiled, but now i realised there's no hardware 3d acceleration (it uses gallium software rendering)
<rajkosto>
guess no way to make that work in linux (only android)
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<KotCzarny>
ssvb: nitehawk: any particular reason why sunxi-tools -m print stops at PI ? on H3 there is also PL block
<smaeul>
I suppose some of these drivers aren't tested much with power management? http://ix.io/z5e
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<NiteHawk>
KotCzarny: I'd have to recheck, but I'm not sure that sunxi-tools has any deeper understanding of the GPIO layout / bank numbers on different SoCs. I think it just uses some "smalles commeon denominator" originating from the early Allwiiner SoCs (A10 to A20).
<KotCzarny>
maybe it should have some soc tables/ranges
<NiteHawk>
that should/could possibly go into soc_info.c, yes
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<mev_>
hi everyone, I'm looking for infos about secure boot on Allwinner/H3. The datasheet is lacking details, could you point me to some resources?
<mev_>
MoeIcenowy chrisf: thank you both, I'm looking :)
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<MoeIcenowy>
but you should note one thing
<MoeIcenowy>
some behaviors are totally different when secure boot is enabled
<MoeIcenowy>
montjoie: I'm retrying dwmac-sun8i on R40
<MoeIcenowy>
(In fact on V40, but R40 and V40 are the same
<MoeIcenowy>
PHY is RTL8211E
<mev_>
I see, like SRAM protection and such
<MoeIcenowy>
the driver seems recognized
<MoeIcenowy>
but when trying to make eth0 up, it says "Could not attach to PHY"
<MoeIcenowy>
/sys/bus/mdio_bus/devices/stmmac-0:01/phy_id is 0x001cc915
<mev_>
just out of curiosity... why does the H3 datasheet misses details about secure boot? security through obscurity?
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<MoeIcenowy>
they hide many things.
<MoeIcenowy>
P.S. the syscon issue is resolved by changing the driver now
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<dothebart>
Should the sunxi driver for the serial console work with r40 chips too? or is there anything special to look at?
<dothebart>
I got the current git u-boot working and start the kernel, however, I don't see any output of the kernel
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<MoeIcenowy>
oh I'm trapped into the same problem twice :-(
<MoeIcenowy>
stmmac_platform.c should also contain r40 compatible
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<MoeIcenowy>
I remembered I made the same mistake when developing for v3s
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<MoeIcenowy>
oh now it shows "eth0: Link is Up - 1Gbps/Full - flow control rx/tx", however, udhcpc eth0 failed
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<dothebart>
MoeIcenowy: are you running a 4.x kernel with working console on serial port?
<MoeIcenowy>
yes, however I have some not-mainlined drivers
<MoeIcenowy>
e.g. CCU driver
<MoeIcenowy>
montjoie: when udhcpc is in definite "sending discover" I unplugged the cable, no link down infomation is shown, however a warning appeared "NETDEV WATCHDOG: eth0 (dwmac-sun8i): transmit queue 0 timed out"
<dothebart>
did you only apply the patches posted on the lkml? or more?
<MoeIcenowy>
the patches posted on LKML is written by me ;-)
<KotCzarny>
but did you apply them?! ;)
<MoeIcenowy>
yes of course ;-)
<MoeIcenowy>
or in fact I'm trying to update them ;-)
<dothebart>
ah, great - talking to the right guy ;-) thanks for your work so far!
<dothebart>
can you share your kernel config? I'm struggling a bit on that part :(
<MoeIcenowy>
does you kernel now totally have no output?
<MoeIcenowy>
try to add earlycon=uart,mmio32,0x01c28000