Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<MoeIcenowy> loblik: I'm doing it
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<Net147> hmm... playing 440 Hz tone on A20 mainline headphone output gives 880 Hz tone
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<Net147> oliv3r: plaes: I do think there is something wrong with the CCU audio clock on A20
<MoeIcenowy> Net147: how about non-CCU old clock drivers?
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<Net147> MoeIcenowy: it was working fine if I remember correctly
<Net147> MoeIcenowy: I think maybe the offsets are incorrect
<MoeIcenowy> it's possible
<Net147> MoeIcenowy: for n and m in pll-audio-base
<MoeIcenowy> CCU drivers are big work and it's easy to be wrong
<Net147> okay, compiling and testing...
<MoeIcenowy> you can check the user manual
<MoeIcenowy> errors are easy to find
<Net147> MoeIcenowy: the manual isn't always right
<MoeIcenowy> But if somewhere the data is different with user manual without any comments
<MoeIcenowy> there's only two possibilities
<MoeIcenowy> 1. the author forgot to put a comment that the manual is wrong
<MoeIcenowy> 2. the data is wrong
<Net147> or it was just copy and pasted from another SoC
<Net147> MoeIcenowy: "Post-divider for pll-audio is hardcoded to 4" in ccu-sun4i-a10.c but in the user manual PLL2_POST_DIV is 0x2 by default
<Net147> MoeIcenowy: changing PLL2_POST_DIV using devmem2 from 0x2 to 0x4 makes the audio output correctly
<wens> the clk driver needs to program it in the probe/init function
<wens> we do that for all of our new ccu drivers
<Net147> wens: do you have a reference to example I can look at?
<Net147> wens: oh I see it now
<Net147> it is writing to undocumented bits in the register...
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<wens> Net147: yes that's it
<Net147> wens: those bits are undocumented... even for A13
<wens> Net147: I think it's the doc that's wrong, but you'll have to dig through the ML archives to find the discussion
<Net147> wens: right. but toggling bits 16-19 on A20 has no effect on the audio for me
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<wens> the doc is wrong only for sun4i/sun5i
<wens> so for A20 you have to toggle the documented post-div bits
<wens> I'm not sure really, but you could give it a try
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<Net147> wens: I did try it. toggling the documented post-div bits works.
<wens> ok?
<Net147> yes, it works fine on A20 now
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<terra854> No one is working on DRM for A64?
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<Net147> wens: in non-CCU clock driver - clk-a10-pll2.c:36:#define SUN4I_PLL2_POST_DIV_SHIFT 26
<wens> Net147: right, and we use that driver on sun4i and sun7i
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<Net147> wens: I can't actually find the discussion where the doc is wrong for A13. there is no comment in the code that the doc is wrong.
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<Net147> wens: in sunxi-3.4, arch/arm/mach-sun5i/include/mach/ccmu_regs.h has struct __CCMU_PLL2_AUDIO_REG0008 and bits 16-19 are in the PLL2 bias current field
<marble_visions> hi all, does kernel 3.4 support device trees?
<Net147> mripard: did you test the audio clock on A13 when you added the sun5i CCU driver?
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<wens> Net147: I think the discussion either happened on IRC, or in private
<wens> MoeIcenowy: pinctrl changes have shown up :)
<wens> montjoie: so I think the solution is "phy-is-internal", maybe wait a few days, then you can send patches fixing dwmac-sun8i?
<montjoie> wens: rockchip patch with phy-is-internal sent this morning, we will see what netpeople will say
<montjoie> at first agreement I will sent patch:)
<wens> :)
<wens> montjoie: btw, next time you send patches, please specify which patches should go in which tree
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<montjoie> I agree
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<plaes> Net147: thanks for another great fix
<Net147> plaes: no problem =)
<oliv3r> plaes: i haven't checked into the why yet, but its quite audioable :)
<oliv3r> why isn't fdt_high not in the sunxi default environemnt? whats the advantage of not having it in there? i just noticed that we always need to set it pretty much, so people who may not need it can override it if needed, rather then almost everybody having to set it, right?
<Net147> oliv3r: "audible"
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<oliv3r> Net147: :p
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<Net147> oliv3r: maybe my patch fixes your double rate audio issue as well?
<wens> oliv3r: I think newer U-boot works without fdt_high?
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<Net147> is there any benefit to copying the FDT on boot?
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<oliv3r> Net147: are they ontop of pleas' patches?
<Net147> oliv3r: I posted a fix for the pll-audio clock in reply to plaes' CCU patchset v6
<Net147> oliv3r: I CC-ed you
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<oliv3r> Net147: ah awesome :)
<oliv3r> i'll test it out yeah
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<oliv3r> what's the cheapest sunxi board?
<oliv3r> orange pi zero?
<KotCzarny> yeah, 256M version
<KotCzarny> 7usd+shipping (~4usd for me)
<loblik> I guess so. I just got it for something like 11usd
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<loblik> but that was 512mb version
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<KotCzarny> opi0(256) costs 6.99usd, opi0(512) 8.99usd in xunlong's store
<KotCzarny> unless you get some crazy promo selling under the original price you won't find cheaper
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<oliv3r> yeah opi0 is very cheap i noticed
<oliv3r> and has quite a lot of cool features
<oliv3r> h2+ is based on A33 right?
<oliv3r> how complete is our support here?
<oliv3r> 6.99 .that
<oliv3r> that's really crazy cheap
<oliv3r> buy 100 of them and you get free shipping? :p
<oliv3r> 4.18 USD shipping though
<oliv3r> gets a little bit cheaper if you get more
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<IgorPec> h2+ = H3 (more or less)
<oliv3r> yeah, wihtout hdmi and gigabit
<oliv3r> but h3 is a33 based right? i mean it's all sun7
<oliv3r> sun8i
<loblik> I'm using armbian with kernel 4.11.3 and there is no throtling so it get's little bit warmer and no wifi as there is no in-kernel driver I guess.
<wens> oliv3r: sun8i = all cortex-a7
<wens> oliv3r: nothing else :p
<loblik> but otherwise this cheap board works quite well atleas so far
<oliv3r> wens: so it no longer refers to the peripherial set?
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<KotCzarny> oliv3r: h3 is quite well supported
<KotCzarny> but opi0 itself is very limited in ports
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<lvrp16> advertising h3 as anything over 1 ghz is a stretch just like raspberry pi 3's 1.2ghz is a stretch
<lvrp16> and the amlogic 2ghz nonsense
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<KotCzarny> lvrp16: with proper design 1.2 is stable on h3
<KotCzarny> even 1.3 (as armbian folks say)
<lvrp16> it's a 1ghz silicon at best
<lvrp16> they've improved it in h5 so you can do 1.2ghz
<wens> MoeIcenowy: are you going to resend the ethernet alias fixes?
<KotCzarny> lvrp16: some xunlong's boards do very good heat dissipation
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<oliv3r> KotCzarny: i see ; actually a lof of our chips are getting to a point where they are quite well supported
<oliv3r> KotCzarny: yeah but i'm sure you need a beefy heatsink
<lvrp16> xunlong uses the oldest h3 design with the programmable i2c regulator, the newer designs skip it in favor of fixed voltage like the banana pi m2+, higher than 1ghz is really an overclock of the silicon.
<oliv3r> and since most are sold without, those boards should be 'safe' at 1ghz
<KotCzarny> lvrp16: they also use a lot of copper in the boards apparently
<oliv3r> so a hidden heatsink of sort s:)
<KotCzarny> and the boards itselves are big
<oliv3r> heat spreader really
<lvrp16> i highly doubt that they use any more than normal
<KotCzarny> opipc+2e/opipc+ i have hardly need any heatsink
<MoeIcenowy> wens: still thinking
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<lvrp16> has any1 played with the h6 yet?
<KotCzarny> no devices released yet
<MoeIcenowy> orange pi says they're doing H6
<MoeIcenowy> on Orange Pi 3
<KotCzarny> lol
<KotCzarny> they should really start including soc in the model's name
<lvrp16> yeah seriously, i recommended that to steven 2 years ago
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<[TheBug]> lol especially with the vartions of the same board with both H3/H5
<[TheBug]> seems it would be logical...
<lvrp16> i hope the h6 has the crypto extensions for the cores
<lvrp16> otherwise it'll just be an 905
<KotCzarny> maybe they've licensed it? ;)
<lvrp16> i couldn't find it on the brief
<MoeIcenowy> I think all A53 has AES instruction set...
<lvrp16> you have to license it separately
<lvrp16> s905 vs s905x
<MoeIcenowy> lvrp16: ?!
<MoeIcenowy> s905 has an A53 without AES?
<lvrp16> s905 doesn't have crypto extensions
<MoeIcenowy> do you mean AES/SHA instruction sets
<MoeIcenowy> or some hardware IP block?
<lvrp16> i mean the instruction support in the A53
<lvrp16> not separate crypto engines
<MoeIcenowy> oh...
<lvrp16> separate crypto engines perform like crap and aren't MT capable
<KotCzarny> mmm, multistream speedup
<MoeIcenowy> if my memory is right H5 has crypto instructions
<MoeIcenowy> yes the "features" in the /proc/cpuinfo on a kernel running on Orange Pi Prime (H5) says "fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid"
<lvrp16> i hope h6 is the same way
<lvrp16> s905x has 1.5GB/s aes throughput on all 4 cores...without it, you have like 20MB/s
<lvrp16> s905 can only do a pathetic 20MB/s
<KotCzarny> mmm, smmmoking!
<lvrp16> on all 4 cores, you can do ~80MB/s
<lvrp16> so if h6 doesn't have it, it'll be really hamstrung
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<MoeIcenowy> is Amlogic the only vendor known to cut the crypto extension?
<lvrp16> in so far as i know, only s905 doesn't have it and h3, h6
<lvrp16> rockchip 33x all have it
<KotCzarny> h3 use a7 cores
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<lvrp16> i should make an 8890 board ;)
<lvrp16> would u guy pay $200 for it?
<lvrp16> guys*
<KotCzarny> allwinner is about lowest cost possible ;)
<KotCzarny> orders on sub 10usd boards from xunlong seems to confirm that
<lvrp16> they're a public company, they really need a breakout chip and not try to live off their 3 year old design
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<lvrp16> otherwise they may go "unpublic" lol
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<willmore> lvrp16, A64 has crypto, right?
<lvrp16> yes
<willmore> Rpi3 seems not to have them either.
<IgorPec> here are some numbers done with H5. https://forum.armbian.com/index.php?/topic/4530-nanopi-neo2-411-kernel/&do=findComment&comment=35173
<willmore> Can you use the AES extension from ARMv7 anyway?
<MoeIcenowy> seems yes
<MoeIcenowy> but I think many programs just doesn'
<MoeIcenowy> doesn't support this configuration
<lvrp16> this doesn't mention it though
<MoeIcenowy> In fact there's still no any record for an Allwiner SoC with A53 without crypto extension
<MoeIcenowy> for H5 I'm sure
<willmore> IgorPec, that's not using the AES extension?
<MoeIcenowy> and for A64 I remember the AES extension is also present.
<IgorPec> willmore: hmm, its stock, but it looks accelerated to me
<lvrp16> it's really confusing with the 4 stream crypto hardware engine vs the arm instructions
<willmore> <70MB/s?
<KotCzarny> hey, dont give them any ideas for H5+ which will be cut down h6 ;)
<IgorPec> willmore: aes-128-cbc 14996.45k 21250.65k 23902.98k 24610.47k 24835.41k 24816.30k
<IgorPec> willmore: aes-128-cbc 102553.09k 274203.39k 458378.92k 569923.93k 613326.85k
<willmore> IgorPec, that's slow.
<IgorPec> first is a20, second is h5
<lvrp16> IgorPec: any results for h3/a64?
<IgorPec> moment
<IgorPec> aes-128-cbc 13756.31k 19608.11k 25561.09k 25972.39k 26105.17k
<IgorPec> h3
<willmore> IIRC, openssl doesn't tend to use AES extensions because they can be vulnerable to certain attacks. You have to tell it when you build it not to worry and use the ISA extensions.
<KotCzarny> hmm
<KotCzarny> igorpec, that's single core results?
<IgorPec> sorry, wrong ... cpu governor is notok
<IgorPec> the same. huh
<lvrp16> a64 should have the instruction extensions, they mention 3-10x software encryption boost
<MoeIcenowy> h3 doesn't has AES extension
<IgorPec> It's Linux nanopineo 4.10.0-sun8i
<MoeIcenowy> AES extension is in fact introduced in ARMv8
<IgorPec> than its ok.
<azelha> hi. anyone know how to setup basic timers and interrups on soc A20?
<MoeIcenowy> how can Cortex-A7 which is ARMv7 have it? ;-)
<MoeIcenowy> azelha: refer to the user manual.
<azelha> A20 user manual dont show all
<azelha> show me info about the gic on A20 mamual
<azelha> should be a sample code of it on sunxi
<willmore> MoeIcenowy, If you mean my comment, I was talking about the Rpi3 which is an ARMv8 chip running in 32 bit mode. I was curious if the AES extensions are available in the 32bit mode. I may have misspoke when I asked my question, sorry.
<MoeIcenowy> willmore: I think it can be present
<MoeIcenowy> check your /proc/cpuinfo
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<MoeIcenowy> and I think many program won't consider ARMv8 AArch32 situation...
<willmore> MoeIcenowy, that was my expectation as well.
<willmore> I don't have a Rpi3 handy to check. But it doesn't have AES anyway, so ...
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<phipli> Hey folks - anyone know what interface(s) the Orange Pi NAS Expansion board connects to on the Orange Pi?
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<phipli> thats the fellow
<phipli> wondering if they are connected to a USB bus, or something better...
<KotCzarny> usb and other pins exposed
<phipli> looking at cnx-software it seems to suggest that the sata is through a USB bus
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<KotCzarny> yes, but those interfaces are existing on h3 chip and just routed
<ElBarto> H3 doesn't have sata so it's 100% sure that it is usb
<KotCzarny> yes, we all know that, but all it exposes on that 13pin is routed to h3
<phipli> ElBarto: keep hoping - still kind of useful expansion though. Good to know it exists if I want to stick a msata and a computer in a tiny box
<KotCzarny> i dont remmber exactly, but i think its jms578 (good one)
<ElBarto> KotCzarny: yes, and ?
<KotCzarny> ~40MB/s r/w
<phipli> KotCzarny: in real world stuff? That's pretty good
<KotCzarny> and since it's uasp it's not that bad in random io too
<KotCzarny> yes, as long it's the chip i think it is
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<willmore> It's also one USB<>SATA per USB bus, so they shouldn't interfere with each other at the hardware level. I can't speak about the driver and block layers.
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