<Rafael1980>
in build kernel you should see the sun8iw8p1smp_zero_diy_defconfig
<apritzel>
this is quite outdated, for ancient versions of Linux
<Rafael1980>
im the new guy in the hood
<apritzel>
I suggest to change to mainline, this is much cleaner and you get more help from people
<apritzel>
Rafael1980: mind the fat disclaimer at the beginning of this page
<Rafael1980>
yeap
<apritzel>
then all you need is a .dts file, which should be the same for both the kernel and U-Boot
<apritzel>
for the kernel you are done (use the existing sunxi_defconfig or multi_v7_defconfig)
<apritzel>
for U-Boot you need a rather simple <your_board>_defconfig in configs/
<apritzel>
Rafael1980: V3s?
<Rafael1980>
V3s
<apritzel>
so I suggest you copy from LicheePi
<Rafael1980>
can you give the link for the mainline
<Rafael1980>
yeah i see that too
<apritzel>
git.kernel.org ;-)
<Rafael1980>
AFAIK the dts file need to be generate and is according to the hardware is used
<apritzel>
you could actually have some success already by just using a LicheePi build
<apritzel>
yes, the .dts describes how the board uses the SoC: which peripherals are used, using which pins, and how the external regulators are connected
<Rafael1980>
I already dowload the u-bbot and kernel for mainline
<apritzel>
reading one should give you some clue
<Rafael1980>
has LInaro for toolchain
<Rafael1980>
buildroot2018
<apritzel>
if you a fairly recent distro on your PC, you could just use the cross compilers provided using in the normal repositories
<Rafael1980>
thanks for the tip I will check it
<apritzel>
Rafael1980: to summarise my rubbish typing: apt-get install gcc-arm-linux-gnueabihf
<Rafael1980>
im using opensuse
<Rafael1980>
Linaro is fine
<Rafael1980>
buildroot too
<Rafael1980>
I use it to do something in fpga
<Rafael1980>
building xilinx kernels
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<Rafael1980>
to do that I needed the dts file
<Rafael1980>
sorry to ask but how can I generate the dts file for the V3s
<Rafael1980>
normally in fpga is the combination of the .mss and .xml file
<Rafael1980>
but in arm no clue
<apritzel>
as I said: you copy an existing one and adjust that to your needs
<apritzel>
I'd start with stripping it to the bare minimal, just serial, for instance
<apritzel>
the adding stuff like MMC and USB
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<apritzel>
the main thing is to find the regulators and describe them
<apritzel>
so how does board provide power for the SD card and USB, for instance
<apritzel>
if you are lucky, this is either not needed or just a GPIO
<apritzel>
the sun8i-v3s-licheepi-zero.dts looks fairly simple, so chances are it actually works without changes
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<Rafael1980>
im looking the dts file and is very simple
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<Rafael1980>
the sd card uart0 usb
<Rafael1980>
if i need the ethernet I need to add this tiem to the dts
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<catphish>
morning
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<catphish>
jernej: if you're around some time and don't mind, i have some questions, probably endless questions, but i'll try to limit them :) the biggest of which being about clock speeds, i want to do 1080p@60 which requires a pixel clock of 148.5MHz, but at what speed should i actually run my PLL?
<catphish>
i get the impression it should be a 297MHz clock with a /2 divider somewhere, but i can't see where the division takes place
<jernej>
check kernel driver - PLL should run with at least 192 MHz, so yes, you should take 297MHz / 2 combination
<jernej>
divider 2 is burried in HDMI PHY code
<catphish>
so run the PLL at 297 and divide by 2 in HDMI_CLK_REG?
<jernej>
take a look at Linux driver, it is more readable
<jernej>
no, divider in HDMI_CLK_REG doesn't have any effect
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<catphish>
oh, the PHY does the division? what about the rest of the HDMI module?
<jernej>
I tested various combinations and it seems that HDMI_CLK_REG divider doesn't have any effect
<jernej>
clocks here are a bit unclear
<jernej>
most importantly, HDMI PHY has to run at target pixel clock
<catphish>
ok, and this is done using the internal divider? (configured with the magic constants)?
<catphish>
PHY_PLL_CFG1 and PHY_PLL_CFG2
<jernej>
as I said, take a look at Linux HDMI PHY driver, there is much less magic constants
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<catphish>
well thats plenty to read, thanks
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<catphish>
it's frustrating that i get zero feedback about whether i'm on track or not until everything works and a get video on screen, but i feel like every day i'm understanding it better, so hopefully it'll fall into place
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<catphish>
jernej: thanks for all your help, my display driver now works :) albeit with a lot of hardcoded values and only a blue test card output, much happy
<catphish>
i was able to crack it in the end by taking a different approach, booting via u-boot and testing each part of my init code until i found the line that broke u-boot's working config, turns out the main problem was that i was forgetting to divide the TCON clock :)
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<Rafael1980>
I guess I can make a menuconfig in the u-boot folder and set those parameters and thenn make a
<Rafael1980>
savedefconfig
<Rafael1980>
is correct?
<jernej>
catphish: I'm glad it works
<catphish>
jernej: it means i won't be bothering you over christmas :)
<jernej>
no worries
<jernej>
I'm a bit surprised how little registers you have to set :)
<jernej>
btw, your code wouldn't work if you would like to change resolution
<jernej>
there is a bug in HDMI controller
<catphish>
i read something about users being unable to change their resolutions in linux
<jernej>
ah, it's not that you can't change, but it shows magenta line at border
<catphish>
that's really interesting, because when i was testing booting with u-boot then re-initializing with my own code, i got a red line down the left
<catphish>
i couldn't explain it
<catphish>
but it went away when i only initialized once
<catphish>
i don't think my code will ever need to switch resolution, i will either hardcode 1080p (because my target is TVs) or i will detect the supported resolution at boot and stick to it, worth knowing the workaround though
<catphish>
oh, the overflow condition, i saw that code, i didn't know if/when i'd need to execute it
<catphish>
well thanks once again for your help, i still don't *really* understand how the HDMI block is pixel-clocked
<catphish>
but i at least know how to select the clock for the PHY, and that seems to be enough
<catphish>
i can only assume the remainder of the HDMI block is clocked via the PHY's PLL
<catphish>
and as long as that matches the clock of the TCON, it's happy
<catphish>
the only part of the code i didn't implement was the video packetizer, the defaults seem fine
<jernej>
I'm not sure either and I studied it much longer than you :)
<catphish>
well my work is mostly just a poor immitation of yours! but it will serve my needs nicely
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<catphish>
now to have some fun wiith the DE
<jernej>
that shouldn't be hard
<jernej>
just be sure that you zero out important ranges even if there is no register documented
<jernej>
I was a bit puzzled why code doesn't work after I tripple checked (or more) all register values
<BroderTuck>
catphish: I see that you're making progress! When I try your latest code from your github my hdmi tv turns blue for a few seconds, and before that the led at PA15 is toggled. Does anything happen for you if you try toggling the LED at PL10 instead?
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<catphish>
BroderTuck: firstly, that is exactly what is supposed to happen currently, so glad to hear it, it blinks A15, then outputs a blue test screen for 4 seconds, then reboots
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<catphish>
should be trivial to blink another LED, i'll try
<catphish>
BroderTuck: L10 doesn't work, might be an issue with my PORTL code, i hadn't tested it
<BroderTuck>
Ok, so it's just not on my device PL10 doesn work, good to know.
<catphish>
i'll check the code now
<BroderTuck>
PORTL is written in the dts as r_pio 0, rather than the pio that the earlier pin banks use, so I guess there's something special that needs to be done for it to work. I have no idea what, tho.
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<catphish>
yeah, PORTL is accessed differently from the others, my code is supposed to already handle that, but i guess i made a mistake
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<catphish>
i'm really not sure why that doesn't work :(
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<smaeul>
catphish: did you set up the clocks/reset for the R_PIO controller?
<smaeul>
it's a second copy of the PIO IP block
<catphish>
smaeul: nope, i'm just checking that now to see if there's gating for it
<catphish>
ah here we go, there is :) i'll sort that out now
<catphish>
thanks
<catphish>
this is almost certainly a clocking problem, but i can't find a clock setting for R_PIO
<BroderTuck>
I'm trying to verify if the second led is really on PL10 on my device (it's not a dev board, so no schematics available, and the fex file is buried on the nand, which mainline linux wouldnt be able to read)
<catphish>
BroderTuck: i'll shout as soon as it works on my board, where it definitely is on PL10
<Rafael1980>
can I use this defconfig to build the kernel for the V3s?
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<BroderTuck>
Rafael1980: I think so yes. Last time i checked, the sunxi_defconfig was missing CONFIG_USB_STORAGE tho, depending on your use case this might be something you want enabled
<Rafael1980>
so ..to resume..to be able to make a SD card to boot the V3s I need to do: 1) build u-boot make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- LicheePi_Zero_defconfig.....to build the kernel make ARCH=arm sunxi_defconfig---build the sunxi-tools (just make inside folder) and build rootfs using buildroot (do I need a dts here)?? is thhose steps correct? miss something in the way?