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<Net147>
jernej: I noticed on A64 that 4.20-rc7 kernel sometimes only reads part of the HDMI EDID not the whole EDID if HDMI is also enabled in U-Boot 2018.11. as a result the resolution is incorrect. any ideas?
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<karlp>
apritzel: where do I set that? (and plaes has the opi zero, I only have the nanopi duo2)
<apritzel>
karlp: either you overwrite the constant in the "clock_set_pll1(CONFIG_SYS_CLK_FREQ);" line
<apritzel>
or you set this symbol in the .config, for instance via make menuconfig, under the "Boot images" submenu
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<plaes>
apritzel: oh wait.. DRAM_CLK does not affect it?
<apritzel>
plaes: DRAM_CLK is independent
<apritzel>
the difference is that now the DRAM init runs with a higher *CPU* clock frequency
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<apritzel>
42 times higher, actually
<plaes>
ok, I was wondering why you had 1008MHz as default :P
<plaes>
yup, works fine with 408MHz
<apritzel>
plaes: in general lowering DRAM_CLK tends to paper over other issues, like wrong DRAM timing settings
<apritzel>
plaes: 1008 MHz is the default CPU frequency for most SoCs
<plaes>
apritzel: anything else you want me to test?
<apritzel>
plaes: I guess reverting the patch works for you as well?
<plaes>
yes
<apritzel>
plaes: OK, thanks
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<jaganteki>
plaes, try to enable DM_USB_GADGET for musb breakage
<karlp>
apritzel: yep, that boots fine with it set to 408. fails at 1008 and 808. (where did you get 408 from? why so specific?)
<apritzel>
karlp: thanks
<apritzel>
karlp: 408 is the default "safe" frequency according to the H3 manual
<karlp>
608 detects (wrongly) 1024 meg, but boots ok.
<apritzel>
I tried to "bisect" some frequencies, but didn't get much higher than 408
<karlp>
are clocks not turned on before ram?
<plaes>
jaganteki: doesn't help :(
<plaes>
wait, sorry
<plaes>
need to prefix with with CONFIG_
<plaes>
/home/plaes/code/u-boot/drivers/usb/gadget/udc/udc-uclass.c:52: undefined reference to `dm_usb_gadget_handle_interrupts'
<apritzel>
karlp: the BROM sets up the basic clocks, but runs the CPU at 24MHz, for the beginning
<apritzel>
karlp: the existing code (before Olliver's patch) ran the DRAM init still with this clock
<apritzel>
karlp: do you want to resend with an amended commit message?
<karlp>
apritzel: I can amend the patch if you like, but can you write the summary you want to see there then?
<karlp>
I'm also happy if you post an alternative revert yourself.
<apritzel>
can do, will just keep your authorship, so shouldn't make a difference
<karlp>
I'm not fussed on being author of a revert :)
<beeble>
karlp: add a schottky diode in series on the rx line (board side) if there is no PU on the cpu side add a 1 to 10k too
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<karlp>
at home, on the usb3 hub I've been using, it works ok, I get all power through a microusb and the usb power monitor, but the work laptop setup powers through the usb-serial.
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<apritzel>
beeble: do you know how long a PLL typically needs to lock to its target frequency? Is this more micro- or milliseconds?
<apritzel>
after tuning the CPU clock PLL to 1008 MHz in the Allwinner SPL code, we wait a mere 400 CPU cycles at 24 MHz, which sounds a bit short to me
<karlp>
is there not a bit to check for the pll being locked?
<karlp>
that's we do in cortex-m land at least... (but we also have docs on what bits are what I guess....)
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<apritzel>
karlp: yes, "modern" SoCs have this
<apritzel>
but this routine seems to cover also older parts like the A20
<karlp>
ahh. joys
<karlp>
do you reckon it's still bit 28? or do they _reallllly_ mean "unimpelemtned" not just "undocumented"
<catphish>
KotCzarny: orange pi one, largely because it was what i could easily source locally
<KotCzarny>
fine choice, ethernet on board
<KotCzarny>
:)
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<catphish>
it's probably the simplest of the orange PIs, half gig of ram, not much voltage control, 100Mbit ethernet, but it's all i need for what i'm playing with
<KotCzarny>
nah, opi0 is even more cut down
<catphish>
oh yeah that's true, no hdmi on those though :(
<KotCzarny>
and keep in mind that even simple voltage control is nice if you dont need much cpu
<KotCzarny>
which allows cooler board
<catphish>
yeah i'll probably leave it running at low speed anyway
<catphish>
will see how i get on
<catphish>
you guys weren't kidding about DRAM being complicated, i tried to start configuring it last night, didn't get very far :)
<apritzel>
karlp: aargh, CC:ed everyone and his dog, but forgot you :-(
* karlp
loves these non-hdmi boards.
<karlp>
apritzel: I don't mind :)
<karlp>
thanks for picking this up
<catphish>
non-hdmi boards are super neat if you only want GPIO
<catphish>
as soon as i enabled the DRAM PLL, things started getting weird, then i fell asleep :) will try again tonight
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<karlp>
well, I want more than gpio, I just don't need a screen :) I want the processing power and cheapness
<catphish>
plenty of uses for a zero indeed, robots in particular
<KotCzarny>
since soc already supports it, adding hdmi jack doesnt add much
<beeble>
apritzel: "depends". time is dependent on the input clock frequency and the internal build up. so the safe bet if unkown is to be in the milliseconds. typically it's in the us range
<KotCzarny>
and allows a lot of additional uses
<karlp>
KotCzarny: yes, but it gets in the way physcially.
<KotCzarny>
mhm
<beeble>
apritzel: and also be aware that sometimes the lock bit on allwinner socs are just timers that set the bit after a timeout (iirc)
<catphish>
hopefully later today i can figure out this DRAM clock mess
<karlp>
beeble: wat :)
<karlp>
that's...... crazy
<KotCzarny>
you get what you pay for
<KotCzarny>
;)
<apritzel>
beeble: really? thanks anyway
<apritzel>
beeble: I did a quick test and indeed the 400 cycles were too short
<apritzel>
given there is at least some sense in the lock bit ;-)
<beeble>
apritzel: not 100% sure if it was allwinner or another chinese chip vendor. mixing up a lot of stuff at the end of year
<beeble>
but if it's crazy it's usually allwinner :)
<apritzel>
beeble: agreed ;-)
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<catphish>
what clock does the cpu use by default?
<catphish>
oh, got it, 24MHz osc
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<apritzel>
karlp: a naked readl loop takes 136 iterations until bit 28 becomes 1, the sdelay(200) in the code before reduces this only to 101 iterations
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<mru>
rockchip is best, their rtc has a 31-day november
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<apritzel>
the commit message is hilarious
<KotCzarny>
truly.
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<tautologico>
catphish: you should write a blog about your baremetal explorations on allwinner SoCs
<KotCzarny>
wiki is better
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<tautologico>
yeah, probably. any way to document this stuff
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<sparks1x>
Hi ^^
<catphish>
tautologico: i can certainly do so, i really feel like i'm just regurgitating what linux does perfectly well, but perhaps others will be interested in small bare metal code like me
<catphish>
tautologico: tonight i'll attack the DRAM PLL, once i have the DRAM and graphcs working, i'll write some blog :)
<KotCzarny>
catphish: since i'm also interested in simple dram bringup, dont be shy!
<KotCzarny>
(on H3)
<catphish>
i'm currently targetting the a20, but i feel like it might be a dying breed and since i have an h3 on my desk now i'm tempted to make the switch
<KotCzarny>
graphical bios running on openrisc core? why not ;)
<KotCzarny>
a20 is nice if you need mobility
<KotCzarny>
battery suport is very handy
<catphish>
i tried to enable the PLL for the dram last night, as soon as i did my A20 went into an inexplicable infinite loop, i'll get back on it shortly, i might just have been lacking sleep
<catphish>
h3 is the better platform what what i hope to achieve anyway, so i'll switch
<tautologico>
I'm on H3 too
<catphish>
i'm worried i'll have to start over on the graphics output (DE2 vs original DE)
<tautologico>
there are lots of resources about baremetal on the rpi
<tautologico>
there should be stuff about baremetal allwinner too
<catphish>
well i can certainly get writing
<catphish>
i'm pretty familiar with the a20 now and hopefully the h3 will be the same in many ways
<KotCzarny>
yeah
<KotCzarny>
they are similar
<KotCzarny>
evolutionary build up
<mru>
similarly lacking in docs, yes
<KotCzarny>
then came h6 and they broke everything
<catphish>
lol
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<KotCzarny>
bbl
<catphish>
i like the look (and price) of the h3, quad core is a nice bonus
<mru>
I have a few here
<mru>
mostly they do what they're meant to
<catphish>
lol that's a good start
<catphish>
this board doesn't seem to have a reset button which is mildly annoying
<tautologico>
which one?
<catphish>
orange pi one
<tautologico>
right, that's the one I have too
<catphish>
there's not even a RST on the GPIO breakout
<catphish>
well i'll live :) i'll just try not to keep crashing it
<tautologico>
power adapter with on/off switch :)
<catphish>
i'll be powering from the OTG port i hope
<catphish>
there's also a power button, so can probably long press tat
<catphish>
*that
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<tautologico>
I don't have an A20 to test your current code
<catphish>
well initially everything i did was dependent on u-boot, now i'm aiming for genuine bare metal
<catphish>
i don't really have anything much to present or to ask yet :)
<catphish>
but will pester people here with questions as i go along i'm sure
<tautologico>
that's why it would be good to have a permanent record of this information, instead of it being lost in IRC logs
<apritzel>
how is "bare metal" documentation different from other documentation?
<apritzel>
I mean clocks are clocks and registers are registers ...
<catphish>
apritzel: that was my feeling to, but i'm happy to contribute some basic code examples for people who might want to do similar
<tautologico>
in the end it's the same, but I think that the only documentation righ tnow is the linux code and the allwinner manuals that only list the registers
<karlp>
tautologico: don't forget the uboot code.
<catphish>
the wiki has /some/ wordy discussion of how things work, obviously more of that would be nice
<karlp>
doesn't look like barebox has any sunxi stuff at all?
<tautologico>
catphish: also some things are scattered in different pages and it's not always easy to find what you're looking for
<catphish>
anyway, as i said, my interest is in a nice simple low level example, so if i get it all working i'll write it up
<catphish>
seems dram is going to be the hard part
<catphish>
but uboot has plenty of code i can copy
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<tautologico>
yeah I spent some time reading u-boot's NAND flash code and learning about nand, never thought it would be so complicated (raw nand I mean)
<catphish>
ah, yeah, i haven't even considered how i'm going to do persistent storage
<catphish>
most likely i'll only do SD card
<tautologico>
emmc is easier, I think
<catphish>
i actually don't know much about it, there's multiple modes? SPI, MMC, SD? all on the same socket?
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<catphish>
anyway, i worry about dram clocks first :) ttyl
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<apritzel>
from a software POV eMMC and SD are virtually the same
<apritzel>
setup a bit here or there differently
<karlp>
hooray for internal FTLs
<karlp>
head in sand ftw
<plaes>
technically it's software in sand
<KotCzarny>
catphish: no pmic, no reset
<KotCzarny>
;)
<KotCzarny>
but you can write openrisc fw that checks gpio button and resets arm cores
<KotCzarny>
if you want
<KotCzarny>
as long you dont nuke openrisc clocks it will run along
<KotCzarny>
it could even wait for ethernet frames with code and run it
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<catphish>
well the h3 is sufficiently different from the a20 that absolutely none of my init code works :)
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<KotCzarny>
:)
<apritzel>
catphish: really? actually those two are not too far away ...
<KotCzarny>
might be missed clock or register
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<catphish>
i've missed something fundamental, i'm running nothing but a "ldr pc fel-8" and it's crashing
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<catphish>
i guess FEL moved, else this would surely work: "sunxi-fel exe 0xffff020"
<KotCzarny>
missed 0?
<catphish>
you're right, but doesn' make a difference
<catphish>
sunxi-fel exe 0xffff0000 similarly fails, where'd the brom go :(
<apritzel>
mru: yeah, could try this, but this is all pretty tight and changes everytime
<apritzel>
that's why I was thinking that the linker could arrange the functions cleverly, to keep the alignment minimal
<apritzel>
the padding, I mean
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<jernej>
Net147: Try commenting line 562 and 563 here: http://git.denx.de/?p=u-boot/u-boot-sunxi.git;a=blob;f=drivers/video/dw_hdmi.c;h=229bd63c97c8222b3ddbfbbb1985ddca47140a0b;hb=HEAD#l562
<jernej>
I'm suspecting that values here are not correct
<Net147>
jernej: I also notice that 3840x2160 30 Hz not stable for me (image flickers on and off) so I have to use 3840x2160 24 Hz
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<catphish>
cool, got code running happily on the h3 now :)
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<jernej>
Net147: U-Boot code was written before many things were known, so it needs some updates
<jernej>
I plan to do it, just have to find some time
<catphish>
Net147: that's not bad, previously you said you only got 15Hz
<jernej>
but since I don't have 4K screen, someone else will have to test and fix it after that
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<Net147>
jernej: I am testing display using sun4i-drm, not using U-Boot
<catphish>
i also don't have a 4k screen, so can't test the DEBE for you
<jernej>
ah, which version?
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<Net147>
jernej: 4.20 rc7
<Net147>
catphish: 24 Hz on A64, 15 Hz on A20 max
<catphish>
Net147: ah ok
<catphish>
i wonder where the bottleck is
<jernej>
Net147: Allwinner have two different 4K settings for HDMI PHY, depending on SoC revision
<jernej>
maybe that's it
<Net147>
catphish: I tried on A20 switching HDMI source from backend to the internal colorbar generator, still no luck
<jernej>
but currently I can't really tell you where is the difference
<jernej>
maybe over weekend
<catphish>
Net147: that's interesting, must be a limitation of the hdmi interface itself then
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<Net147>
catphish: 3840x2160 15 Hz is roughly same pixels per second as 1920x1080 60 Hz
<catphish>
it is indeed, makes sense
<catphish>
this could just be a limitation of the input clock
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<karlp>
apritzel: oh, I think I understand what you mean now, yeah, I don't know any tricks with ld scripts to do what you want.
<karlp>
where are the vectors defined?
<apritzel>
arch/arm/cpu/armv8/exceptions.S
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<apritzel>
from the linker's POV it's just ordinary code, just with an insane alignment
<karlp>
yeah, but if you just give them their own sections, it will jsut pad as needed to make it start at the right place,
<karlp>
I don't kno whow to re-order sections that don't matter to result in the tightest packing
<karlp>
do they have to go in sram?
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<apritzel>
karlp: that's another plan: they could be somewhere else (other SRAM, for instance)
<apritzel>
but:
<apritzel>
the BROM only loads 32KB into SRAM A1
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<apritzel>
so we would need to copy them
<karlp>
you can make artificial regions of the same ram, basically _always_ reserve the last 2k or something, or always the first 2k?
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<apritzel>
the first 2k don't work, because there needs to be the eGON header
<apritzel>
and there are much smaller than 2K, so putting them at the end would be a waste as well
<mru>
is there any harm in the image being a fixed size rather than the exact size needed by the code?
<apritzel>
mru: the eventual image is padded to 8K anyway
<apritzel>
so: no
<mru>
otherwise, the best I can think of is finding some random stuff you can stuff between the entry code and the vectors
<apritzel>
mru: yeah, I was looking into this
<mru>
maybe a data table or something
<mru>
anything that's not likely to grow
<apritzel>
.rodata and data are a bit above 2K
<apritzel>
maybe I can split this up
<apritzel>
to put the first part right after the header
<mru>
you can take anything from .rodata and put it wherever
<apritzel>
and fill 2K
<apritzel>
one question though:
<apritzel>
how can I say: I want .text, then .data, then .text again
<apritzel>
in the linker script
<apritzel>
does that work?
<apritzel>
as I read it it's per output section
<mru>
the linker doesn't care what's in the sections
<apritzel>
ah
<apritzel>
so I can call the first one .header and still put code in there?
<mru>
sure
* apritzel
goes to divide (and conquer) the .data section
<apritzel>
to find a bit less than 2K ...
<apritzel>
btw: if that works, we can have a single image for multiple SoCs ...
<apritzel>
that works already for A64 and H5, just with a 32-bit FEL
<apritzel>
s/FEL/SPL/
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<apritzel>
mru: shoot, all the strings together are just 84 bytes too large to stuff them into this gap ...