rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<MoeIcenowy> jernej: I think no
<MoeIcenowy> do you really have a half DQ H6 board?
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<jernej> MoeIcenowy: One of LE user has Tanix TX6 mini STB, which I'm pretty sure it has half DQ
<jernej> MoeIcenowy: here is DT: http://sprunge.us/OFjuyh
<jernej> that 1 in dram_para2 means half DQ, right?
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<MoeIcenowy> jernej: do you have PCB photo of it?
<MoeIcenowy> dual sided
<jernej> note that it also uses DDR3, but together with apritzel we added support for it
<jernej> Tanix TX6 (without "mini") uses same DDR3 chips, but it works fine (I have that STB)
<jernej> how do you know if it is half DQ from images?
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<MoeIcenowy> jernej: by the size of the DRAM chips
<MoeIcenowy> jernej: BTW do you remember the 0x03006100 problem?
<jernej> yes, I do
<MoeIcenowy> this is an interesting device -- it uses H6 CV200-OS
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<MoeIcenowy> according to Wink it's some bonding id of the subversion of the chip
<jernej> oh, so it may actually have bonding id 3
<MoeIcenowy> had you observed 0x03006100 difference w/ Pine H64?
<MoeIcenowy> Pine H64 uses H6 V200-AWIN
<jernej> I have to add this printout in next test version
<MoeIcenowy> there're 3 known H6 subversions
<MoeIcenowy> V200-AWIN (seen in Pine H64)
<jernej> no, all devices I have have bonding id 7
<MoeIcenowy> V200-AI (seen in OPi3)
<MoeIcenowy> CV200-OS (seen in this device)
<jernej> do you know what is the difference?
<jernej> between all this variants?
<MoeIcenowy> according to Wink they're selected
<MoeIcenowy> according to the bin
<MoeIcenowy> BTW this board doesn't look like half DQ
<MoeIcenowy> it has 4 8-bit DDR3 chips
<MoeIcenowy> 4*8=32
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<jernej> half DQ would be only when 2 8-bit chips would be used?
<MoeIcenowy> although it's theortically possible to be dual rank 2*8
<MoeIcenowy> but I don't think any OTT vendor will use it
<MoeIcenowy> because half DQ will decrease the decoding capability of the board
<jernej> but why then dram_para2 suggest half DQ?
<MoeIcenowy> due to it halves the memory bandwidth
<MoeIcenowy> jernej: the dram_para is nonsense in FEX
<MoeIcenowy> it will gets overrided in H6 libdram
<MoeIcenowy> if autodetecting is enabled
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<jernej> yeah, I think you're right, autodetecting seems to be enabled
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<jernej> MoeIcenowy: Do you have any description what DRAM parameters in fex represents? I mean bit by bit.
<MoeIcenowy> jernej: no
<MoeIcenowy> but if you want sth
<MoeIcenowy> I can ask Wink
<jernej> yeah, it would be nice to have it explained on wiki
<jernej> MoeIcenowy: How banks fits into DRAM configurations? I see H6 code supports only 8 banks for now, but controller supports also only 4 banks.
<jernej> what are the chances to see 4 banks configuration?
<MoeIcenowy> jernej: check the number of CS (chip select) pin
<MoeIcenowy> on sorry it's rank, not bank
<MoeIcenowy> bank is the case of internal DDR structure
<MoeIcenowy> for all DDR3/LPDDR3 it's 8 banks
<MoeIcenowy> 4 banks is for DDR2
<MoeIcenowy> the V3s DDR2 is 4 banks
<jernej> aha, ok
<jernej> so there is no point to look into that for now
<MoeIcenowy> yes
<MoeIcenowy> and I don't think there would be board w/ H6+DDR2
<MoeIcenowy> H6 is advertised for decoding capability
<MoeIcenowy> use low-bandwidth memory will severely break it
<jernej> true
<MoeIcenowy> in fact I had never seen Allwinner Cortex-A boards w/ dedicated DDR2
<MoeIcenowy> since A10
<jernej> I hope we would see DDR4 based H6 board
<MoeIcenowy> no...
<MoeIcenowy> DDR4 code will be difficult
<MoeIcenowy> DDR4 is more complex than {,LP}DDR3
<jernej> if we cracked (LP)DDR3, we can DDR4 too
<jernej> BTW, yesterday I found definition of DX[0-4].RSR[0] bit in qemu code for Zynq US+
<MoeIcenowy> qemu...
<MoeIcenowy> interesting
<jernej> it just says QSGERR
<jernej> which is kind of expected :)
<MoeIcenowy> but I didn't expect QEMU to have DDR code...
<jernej> I think it's there so unmodified software can run
<jernej> but it's not really needed
<MoeIcenowy> jernej: yes, the current Allwinner emulation in QEMU is too bad
<MoeIcenowy> it even doesn't emulate CCU and the clock driver will fail due to many /0 error on boot
<jernej> I never really used qemu...
<MoeIcenowy> so do I, except for KVM
<MoeIcenowy> (oh I use qemu-user, but rarely qemu-system
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<MoeIcenowy> (I used to run few times RISC-V kernel on QEMU, but after then I switched to HFU
<jernej> MoeIcenowy: Have "Half DQ" configuration influence on DRAM size calculation?
<jernej> e.g. should be size halved?
<MoeIcenowy> yes
<MoeIcenowy> see my comment around the formula
<MoeIcenowy> (in H6
<MoeIcenowy> it says 32-bit (4 byte) data width
<MoeIcenowy> half DQ is 16-bit
<MoeIcenowy> so the *4 should be changed to *2 for half DQ
<jernej> btw, this board has half DQ, because it uses 4 4-bit chips (k4b4g0446q)
<jernej> only issue I have now is that only half of memory is detected (1 GiB instead of 2)
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<jernej> ah, I never really know where that 4 came from :)
<jernej> and yes, that box is as cheap as it can be, it even has XR819
<jernej> MoeIcenowy: Could it be that due to half DQ one column less is detected?
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<MoeIcenowy> jernej: no
<MoeIcenowy> half DQ is a really hardware thing
<MoeIcenowy> column is inside the chip
<MoeIcenowy> jernej: is there really 4-bit DDR3 chip?
<MoeIcenowy> oh there really is
<jernej> MoeIcenowy: in mctl_auto_detect_dram_size() you mentioned that half DQ is TODO. By that you mean mctl_core_init()?
<jernej> I'm just exploring why only half of RAM is detected
<MoeIcenowy> jernej: I think we need to detect DQ at first
<jernej> yes, that's done by first call to mctl_core_init().
<MoeIcenowy> at least before row/column
<MoeIcenowy> and see my comments
<MoeIcenowy> all my formulas assume 32-bit width
<MoeIcenowy> and for half DQ you need to change them
<jernej> yes, but I'm not sure how
<MoeIcenowy> do you see 1<< (blabla + blabla + const) ?
<jernej> yes?
<MoeIcenowy> just let const be 1 less when half DQ
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<MoeIcenowy> oh sorry
<jernej> aha, that's what I thought, but I wasn't sure if it's correct or not
<jernej> ?
<MoeIcenowy> I need to check whether all the consts need to be lowered
<MoeIcenowy> the address is divided into many parts in mctl_set_addrmap
<MoeIcenowy> I had some notes, but they used to be in my laptop's DRAM
<MoeIcenowy> not non-volatile
<MoeIcenowy> so I need to recalculate it
<jernej> uh :(
<MoeIcenowy> let me grab a manual for this IP
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<MoeIcenowy> jernej: bad news
<MoeIcenowy> my poppler breaks
<MoeIcenowy> now I cannot read some PDF
<MoeIcenowy> including i.MX7 reference manual
<jernej> sorry to hear that
<jernej> i.MX7 has useful DRAM info?
<MoeIcenowy> i.MX7 uses the DW DDR controller
<DuClare> MoeIcenowy: Try mupdf
<MoeIcenowy> see the ADDRMAP registers
<MoeIcenowy> it's about mapping the address to different parts of the DRAM
<jernej> I know that libdram decrements number of columns by one if half DQ is detected
<jernej> I'm just not sure if this directly maps to our code?
<jernej> it's shifted by one for half DQ mode
<jernej> brb
<MoeIcenowy> jernej: yes so I think we should consider this in mctl_set_addrmap
<MoeIcenowy> and both consts in mctl_auto_detect_dram_size should be sub 1 for half DQ
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<jernej> ok, thanks
<jernej> now we have to wait for confirmation if this helped or not
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<MoeIcenowy> jernej: it's not your device?
<jernej> no, one LE user has it
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<jernej> MoeIcenowy: with this patch (on top of apritzel's DDR3 series) http://sprunge.us/qDGESm everything works
<jernej> Thanks for help!
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<MoeIcenowy> jernej: why do you change the column switch in mctl_set_addrmap?
<jernej> I reverted this change back
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<jernej> during intial patches it reported invalid number of columns, but now it should be fine
<jernej> *initial tests
<MoeIcenowy> BTW I think your rank/width detect code is still not proper
<MoeIcenowy> oh sorry reading patch is not my advantage
<MoeIcenowy> did you do any regression test on Pine H64?
<MoeIcenowy> BTW in the final version you should remove DXnRSR0 print
<jernej> not yet, probably tomorrow
<jernej> as I said, this is developer version of the patch
<jernej> I will clean it up
<jernej> better version: http://sprunge.us/SEAasY
<jernej> MoeIcenowy: PineH64 4GiB is dual rank and 2 GiB version is single rank, right?
<MoeIcenowy> no
<MoeIcenowy> 4/2 are all dual rank
<MoeIcenowy> 1 is single
<jernej> oh, then I won't be able to do any good regression testing
<MoeIcenowy> jernej: LPDDR3 is a special situation
<MoeIcenowy> it has 2 CS pins per chip package
<MoeIcenowy> as Pine H64 has one footprint
<MoeIcenowy> it depends on the DRAM chip to be 2 ranks or 1 rank
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<jernej> ah, it seems that this latest, cleaned up patch doesn't work, invalid number of columns
<MoeIcenowy> jernej: so how many?
<jernej> final configuration is 11 columns and 16 rows
<MoeIcenowy> final what do you mean?
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<MoeIcenowy> probed in struct dram_para?
<jernej> but it seems that during size detection this number is out of range
<jernej> when it's trying different combinations
<jernej> libdram has that default case instead of 12
<MoeIcenowy> jernej: do we really have any codepath to let cols go beyond 11?
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<MoeIcenowy> when detecting rows we're assuming cols = 8
<MoeIcenowy> and when detecting cols we end when cols == 11
<MoeIcenowy> default is cols = 11
<jernej> not sure how this happens
<jernej> I'll add some debug output
<MoeIcenowy> try to set the default cols to 8 ?
<MoeIcenowy> jernej: I know
<jernej> ?
<MoeIcenowy> we need to add codepath for cols = 7 for full DQ
<MoeIcenowy> which equals = 8 for half DQ
<jernej> so although this is invalid, we have to write something in it, right?
<MoeIcenowy> it's valid
<MoeIcenowy> it's the cols = 8 for half DQ
<jernej> so how to configure when cols == 7? Currently I'm using code for case 12, which seems to work
<jernej> btw, how can we have case 12?
<jernej> maybe it should be 7 in the first place
<MoeIcenowy> yes should be 7 in the first place
<MoeIcenowy> the HW in fact supports 3 to 12
<MoeIcenowy> just append one more 0x1F to the 8 configuration
<MoeIcenowy> compare the configuration between 8 and 9
<MoeIcenowy> you will know
<MoeIcenowy> (one 0x1F means one column line is masked
<MoeIcenowy> `If set to 15, this column address bit is set to 0.` according to the Zynq UG1087
<MoeIcenowy> oh sorry HW supports 5 to 12
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<MoeIcenowy> the lower half of addrmap[2] is forced to 0
<jernej> so case for 12 is ok, I should add similar to that of case 8, with one 1F more, right?
<MoeIcenowy> yes
<MoeIcenowy> addrmap[3] = 0x1F1F1F00; addrmap[4] = 0x1F1F;
<MoeIcenowy> for case 7
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<MoeIcenowy> case for 12 is ok, but not used now
<MoeIcenowy> it's really deadcode
<MoeIcenowy> furtherly we may reach there by setting the upper limit in auto_detect_size to 12
<MoeIcenowy> but we haven't seen such a DRAM chip
<MoeIcenowy> the highest columns number proceeded in H3 code is 10 in fact
<MoeIcenowy> (11 when half DQ
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<MoeIcenowy> jernej: in fact the addressing ability of the DRAM controller is far more than the internal bus of H6
<jernej> I imagine, 3 GiB is not much by today standards
<MoeIcenowy> yes
<MoeIcenowy> I think the internal bus is designed to be 32-bit
<jernej> hopefully next SoC can use more RAM
<MoeIcenowy> they did it on A80
<MoeIcenowy> A80 uses LPAE feature of A7/A15
<MoeIcenowy> and can address 8GiB of DRAM
<jernej> yes, but with 64-bit cores you don't have to do that anymore
<MoeIcenowy> yes
<MoeIcenowy> but I think AMBA components are also sold as IP cores
<MoeIcenowy> and Allwinner may only order 32-bit AMBA cores now
<jernej> I think DE2 and DE3 are ready for 40-bit addresses
<jernej> there is separate register which holds upper 8-bits
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<MoeIcenowy> jernej: interesting
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<jernej> MoeIcenowy: It works with case 7, so final patch is: http://sprunge.us/r0wMfY
<jernej> do you have PineH64 with 1 GiB of RAM to test this patch?
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<z3ntu> Hi, does somebody know how to fix the error `dwmac-sun8i 1c30000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)` ?
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<MoeIcenowy> z3ntu: what SoC and what device?
<z3ntu> MoeIcenowy: A64, pinephone devkit
<MoeIcenowy> did you power up the PHY?
<MoeIcenowy> is the LEDs on the Ethernet port lit up?
<z3ntu> Yes both leds on the port are blinking
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<MoeIcenowy> z3ntu: are you sure your PHY address is right?
<z3ntu> MoeIcenowy: Funnily enough, after applying some patches for dsi and rebooting, ethernet is working now...
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<z3ntu> jaganteki: I'm trying to rebase the pinephone devkit kernel (currently 5.1-rc7) onto 5.2-rc6 using your v10 dsi patch set (and 'dsi: Add has_mod_clk quirk', 'dsi: Add Allwinner A64 MIPI DSI support' & 'a64: Add MIPI DSI pipeline' from v9) but the result is that the display is blinking fast and there's "vblank wait timed out" in the dmesg
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