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20:12
<
megi >
looks like gpu pll on H6 is NKMP clock, and those are implemented in such a way in mainline that they are prone to overshooting the frequency during output divider reduction
20:13
<
megi >
so disabling P divider may help
20:13
<
megi >
or fixing the dividers
20:14
<
megi >
and just allowing N to change
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<
megi >
hmm, I haven't looked at this for quite some time, but H6 BSP way of setting PLL factors actually makes the most sense out of everything I've seen/tested so far
20:23
<
megi >
it waits for lock not after setting NK factors, but after reducing the M factor (pre-divider)
20:24
<
megi >
I might as well re-run my CPU PLL tester with this algorithm, to see if it fixes the lockups
20:26
<
megi >
it makes sense to wait for PLL to stabilize "after" changing all the factors that actually affect the VCO, and not just some of them
20:28
<
megi >
it may be the same thing that plagues the CPU PLL rate changes at runtime
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