<kbeckmann>
whitequark: thanks! that worked. I ran it with --port A before... any reason why B behaves differently?
<whitequark>
kbeckmann: the PLL is attached to one of the pins on port B
<whitequark>
like, it actually *replaces* the SB_IO block, sort of
<whitequark>
it's quite disgusting, really
<whitequark>
and it's deep in a datasheet so you don't even notice it...
<kbeckmann>
haha ok. wow. thanks for figuring it out.
<whitequark>
oh I knew that
<whitequark>
I actually just wanted to use the PLL myself
<whitequark>
btw, take a look at gateware.pll.
<whitequark>
you don't need to use icepll anymore
<whitequark>
this is built into glasgow now
<kbeckmann>
oh, that's awesome!
<GitHub-m-labs>
[artiq] hartytp commented on issue #1198: hmm...yes...so is the preferred solution to add some exception handling to `sync_struct`, which places informative info in the log when exceptions occur? https://github.com/m-labs/artiq/issues/1198#issuecomment-443414758
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1198: The methods that sync_struct calls should not raise exceptions; when they do it is because of internal program errors (which should be debugged the same way as other asyncio problems).... https://github.com/m-labs/artiq/issues/1198#issuecomment-443415226
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1201: I suppose this is because of the ``ret`` clock domain in ``adc_ser.py``; since all the modules in the hierarchy are anonymous or named the same, migen does not know how to rename them when there are multiple ones. https://github.com/m-labs/artiq/issues/1201#issuecomment-443415752
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1201: I suppose this is because of the ``ret`` clock domain in ``adc_ser.py``; since all the modules in the hierarchy are anonymous or named the same, migen does not know how to rename the ``ret`` domains when there are multiple ones. https://github.com/m-labs/artiq/issues/1201#issuecomment-443415752
<GitHub-m-labs>
[artiq] sbourdeauducq commented on issue #1188: @drewrisinger To clarify my position: while i am opposed to using type annotations inside ARTIQ, merging this and having ``pc_rpc`` handle them for user code is totally fine. https://github.com/m-labs/artiq/pull/1188#issuecomment-443417232
<whitequark>
sb0: the tbaa stuff is only used inside of LLVM, it's not expected to be used inside of ARTIQ
<whitequark>
sb0: regarding the return value of process_Builtin, it doesn't terribly matter here, since the return values of at_mu and delay_mu are never used
<whitequark>
the requirement for having every process_* return something is outdated
<whitequark>
it became impossible to do in the way it was intended after I added expansion of IR instructions to multiple LL instructions