sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
cr1901_modern1 has joined #m-labs
<_whitenotifier-f> [nmigen] whitequark edited issue #6: Implement remaining core Migen features - https://git.io/fpbpZ
<_whitenotifier-f> [nmigen] whitequark edited issue #6: Implement remaining core Migen features - https://git.io/fpbpZ
<_whitenotifier-f> [m-labs/nmigen] whitequark pushed 2 commits to master [+1/-0/±5] https://git.io/fpAJx
<_whitenotifier-f> [m-labs/nmigen] whitequark 87cd045 - back.rtlil: implement Part.
<_whitenotifier-f> [m-labs/nmigen] whitequark 8506746 - back.rtlil: implement Array.
<_whitenotifier-f> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/468819901?utm_source=github_status&utm_medium=notification
<_whitenotifier-f> [nmigen] Failure. 76.95% (-0.6%) compared to f968678 - https://codecov.io/gh/m-labs/nmigen/commit/850674637a386f4e5e59ab5b65ab2e8bcc1ae8e3
<_whitenotifier-f> [nmigen] Failure. 0% of diff hit (target 77.55%) - https://codecov.io/gh/m-labs/nmigen/commit/850674637a386f4e5e59ab5b65ab2e8bcc1ae8e3
cr1901_modern has quit [Ping timeout: 250 seconds]
cr1901_modern1 has quit [Quit: Leaving.]
cr1901_modern has joined #m-labs
balrog has quit [Quit: Bye]
balrog has joined #m-labs
rohitksingh_work has joined #m-labs
_whitenotifier-f has quit [Ping timeout: 268 seconds]
_rht has quit [Quit: Connection closed for inactivity]
<rjo> whitequark: there is a wrinkle to the nmigen syntax. if you populate multiple Module()s concurrently, the python indentation context and the per-Module contexts can easily conflict (with m1.If(): .. with m2.If(): ..). inheriting from Module and thus primarily just having the "self" Module context in get_fragmet would make that a bit harder.
<rjo> and less likely to happen.
rohitksingh_work has quit [Ping timeout: 246 seconds]
rohitksingh_work has joined #m-labs
rohitksingh_work has quit [Ping timeout: 272 seconds]
_rht has joined #m-labs
rohitksingh_work has joined #m-labs
<7YUAAKG5J> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/35bdf26f01c94054c4442d4b35e8265493ad6f51
<7YUAAKG5J> artiq/master 35bdf26 Sebastien Bourdeauducq: Merge branch 'ad9910-ram'
<07IAAVK8V> [artiq] sbourdeauducq closed pull request #1208: ad9910: add RAM mode methods (master...ad9910-ram) https://github.com/m-labs/artiq/pull/1208
<GitHub-m-labs> [artiq] sbourdeauducq closed issue #1154: Urukul: expose/wrap/document/test RAM, waveform etc https://github.com/m-labs/artiq/issues/1154
<GitHub-m-labs> [artiq] jordens commented on issue #1208: ```python... https://github.com/m-labs/artiq/pull/1208#issuecomment-447843520
rohitksingh_work has quit [Read error: Connection reset by peer]
<GitHub-m-labs> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/a7d4d3bda9c74e98463fb8893bf251794ce2456a
<GitHub-m-labs> artiq/master a7d4d3b Robert Jördens: ad9910: CONT_RECIRCULATE -> CONT_RAMPUP
<whitequark> rjo: why are you populating multiple modules concurrently?
<rjo> whitequark: i am not, i don't want to, and i don't want anybody to try. but it is made possible and seems to be the intention of the style of instantiating Module in get_fragment().
<whitequark> rjo: the intention is to separate the DSL from the IR, and more so, remove the Module magic from user classes
<whitequark> the former does not serve a major user facing purpose, the latter definitely does.
<bb-m-labs> build #2149 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2149
<whitequark> for example, with your new DSL (which I like!) it is not possible to have a field called "d" in classes that would hypothetically inherit from Module
<whitequark> nor "sync"
rohitksingh has joined #m-labs
<bb-m-labs> build #2150 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2150
<bb-m-labs> build #972 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/972
<bb-m-labs> build #2767 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2767
<rjo> whitequark: yeah. ok. but then we should explicitly point out that populating logic for multiple Module()s concurrently can quickly lead to bad and confusing style.
<whitequark> rjo: agree
<whitequark> rjo: btw. the new Part/Array implementation uses a generic legalization algorithm. so it uses no intermediate signals.
<whitequark> or https://paste.gnome.org/pa5p02xnk i guess.
<bb-m-labs> build #2151 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2151
<rjo> whitequark: isn't https://paste.gnome.org/psgdcojqf#line-75 an intermediate signal? intermediate signal = proxy?
<whitequark> rjo: see the other paste.
<whitequark> this was a failure of namer because there are no records yet
<whitequark> rjo: btw i thought again and i no longer think rec1.eq(rec2) or rec1.eq(sig) should require shape to match exactly
<whitequark> that is inconsistent with the rest of nmigen
<whitequark> there probably *should* be something like .eq_exact (probably different name), for people who value that kind of code style.
<whitequark> but it should be separate.
<whitequark> so, the current idea is to a) make Record a core type, next to Signal, b) assigning to or from a record is the same as .raw_bits()
<whitequark> well, desugars to Cat
<bb-m-labs> build #2152 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2152
<bb-m-labs> build #2768 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2768 blamelist: Robert J?rdens <rj@quartiq.de>
<rjo> whitequark: ok. sounds good. maybe "eq_strict"?
<whitequark> kind of annoyingly verbose
<GitHub-m-labs> [artiq] sbourdeauducq closed issue #1218: PYON Can't Encode NamedTuple https://github.com/m-labs/artiq/issues/1218
<whitequark> maybe it should even be a module flag.
<whitequark> Module(strict=True)
<whitequark> something like "use strict" in JS, which has a similar "stringly typed" problem as migen has a "flexibly typed" problem
<rjo> oh yes. Module can have different rules.
_whitenotifier-6 has joined #m-labs
<_whitenotifier-6> [m-labs/nmigen] whitequark 4de631a - Travis: build and cache Yosys.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469082711?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpAxy
<_whitenotifier-6> [m-labs/nmigen] whitequark 6183f62 - Travis: build Yosys without abc.
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469095524?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpApI
<_whitenotifier-6> [m-labs/nmigen] whitequark e1ea506 - Travis: build and cache Yosys.
key2_ has joined #m-labs
key2 has quit [Ping timeout: 256 seconds]
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469096992?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 76.95% remains the same compared to 8506746 - https://codecov.io/gh/m-labs/nmigen/commit/e1ea506adb911e49ebca6e06404f9b6fad978164
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing 8506746...e1ea506 - https://codecov.io/gh/m-labs/nmigen/commit/e1ea506adb911e49ebca6e06404f9b6fad978164
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469096992?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpAjD
<_whitenotifier-6> [m-labs/nmigen] whitequark 3f05b80 - Travis: build and cache Yosys.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469106209?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 76.95% remains the same compared to 8506746 - https://codecov.io/gh/m-labs/nmigen/commit/3f05b8052113ca525b6104d108eb80255e9186c4
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing 8506746...3f05b80 - https://codecov.io/gh/m-labs/nmigen/commit/3f05b8052113ca525b6104d108eb80255e9186c4
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxvM
<_whitenotifier-6> [m-labs/nmigen] whitequark b783592 - Travis: build and cache Yosys.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469113505?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 76.95% remains the same compared to 8506746 - https://codecov.io/gh/m-labs/nmigen/commit/b783592ace5de24ddc0df1fa8aaa9c96b2f9b4ea
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing 8506746...b783592 - https://codecov.io/gh/m-labs/nmigen/commit/b783592ace5de24ddc0df1fa8aaa9c96b2f9b4ea
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±10] https://git.io/fpxUm
<_whitenotifier-6> [m-labs/nmigen] whitequark 8c4de99 - hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
<_whitenotifier-6> [m-labs/nmigen] whitequark 8d1639a - hdl, back: add and use SignalSet/SignalDict.
<_whitenotifier-6> [m-labs/nmigen] whitequark de6c12a - Travis: build and cache Yosys.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469124814?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 76.84% (-0.12%) compared to 8506746 - https://codecov.io/gh/m-labs/nmigen/commit/de6c12af77044e7277c0cfe7f792d9338f7e28db
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing 8506746...de6c12a - https://codecov.io/gh/m-labs/nmigen/commit/de6c12af77044e7277c0cfe7f792d9338f7e28db
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1219: @drewrisinger please test this patch:... https://github.com/m-labs/artiq/issues/1219#issuecomment-447941035
rohitksingh has quit [Remote host closed the connection]
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±6] https://git.io/fpxa6
<_whitenotifier-6> [m-labs/nmigen] whitequark c7f9386 - fhdl.ir: add black-box fragments, fragment parameters, and Instance.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469263445?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.51% (+0.67%) compared to de6c12a - https://codecov.io/gh/m-labs/nmigen/commit/c7f9386eabaa30a3fb1f5da6e75eb0c7b3668568
<_whitenotifier-6> [nmigen] Success. 88.63% of diff hit (target 76.84%) - https://codecov.io/gh/m-labs/nmigen/commit/c7f9386eabaa30a3fb1f5da6e75eb0c7b3668568
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxoq
<_whitenotifier-6> [m-labs/nmigen] whitequark ccfd930 - Travis: cache Yosys installation explicitly.
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469281799?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxou
<_whitenotifier-6> [m-labs/nmigen] whitequark ffe7c89 - Travis: cache Yosys installation explicitly.
<_whitenotifier-6> [nmigen] whitequark commented on issue #1: Example of embedding exisiting Verilog? - https://git.io/fpxoM
<_whitenotifier-6> [nmigen] whitequark closed issue #1: Example of embedding exisiting Verilog? - https://git.io/fpdHW
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469283303?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.51% remains the same compared to c7f9386 - https://codecov.io/gh/m-labs/nmigen/commit/ffe7c89169dd851bd8f7ca73929ff1e28017e031
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing c7f9386...ffe7c89 - https://codecov.io/gh/m-labs/nmigen/commit/ffe7c89169dd851bd8f7ca73929ff1e28017e031