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<GitHub-m-labs> [artiq] jordens commented on pull request #1204 f23536c: Indentation/tabs/spaces. Please run a linter (e.g. `flake8`). https://github.com/m-labs/artiq/pull/1204#discussion_r238178849
<GitHub-m-labs> [artiq] sbourdeauducq commented on pull request #1204 f23536c: Then the behavior is incorrect. You may want to call ``msvcrt.getch`` on Windows instead (and test for the ENTER key so it's consistent with Linux). https://github.com/m-labs/artiq/pull/1204#discussion_r238179602
<GitHub-m-labs> [artiq] sbourdeauducq commented on pull request #1204 f23536c: The problem is: if the user presses a key other than ENTER and nothing else, then the program freezes.... https://github.com/m-labs/artiq/pull/1204#discussion_r238179942
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<lkcl> does anyone know of an actual RISC core written in migen? (and not GPL or LGPL'd)
<lkcl> most if not all of the migen SoCs i have encountered are verilog wrappers
<whitequark> lkcl: well, i made one yesterday
<whitequark> and i've redesigned it today
<lkcl> whitequark: cool!
<lkcl> already? woow :)
<whitequark> the yesterday's one is kind of crap, i would not recommend looking at it
<whitequark> the redesign is going to be pretty nice
<whitequark> well, it is not technically classifiable as CISC or RISC
<whitequark> but it is sort of RISCy
<lkcl> doesn't matter, i am happy whatever it is
<lkcl> there's concepts that are missing in my tiny brain that i need to get up to speed on
<lkcl> ahh awesome
<lkcl> whitequark, that's a pretty damn efficient use of 16-bit opcode space
<lkcl> sort-of huffman encoding
<whitequark> lkcl: yeah, I spent quite a while on it
<whitequark> it is also optimized for decoding with LUTs
<lkcl> the field lines are regularly spaced, R-rst alwys in the same place R-opa linewise
<lkcl> did you get to the execution unit yet?
<whitequark> I haven't even started gateware for v2
<whitequark> but it'll be FSM-driven
<whitequark> so, effectively microcoded
<lkcl> oo nice
<whitequark> it uses only single port RAM, too
<whitequark> so you could use 256 kB of SPRAM on iCE40UP5K
<lkcl> *sigh* analysing the requirements for the libre-riscv soc i have this scary feeling i'm going to need to implement the tomasulo algorithm with reorder buffers and everything...
<sb0> lkcl: look at minerva
<lkcl> sb0: ahh awesome
<lkcl> sb0: whereabouts? google searches don't find it
<sb0> ah it's not published yet, thought it was
<sb0> let me ask
<lkcl> ok cool
<lkcl> ahh it's florien
<sb0> no
<lkcl> oh? ahh, someone else. ok
<cr1901_modern> wait is minerva an out of order core?
<sb0> o
<sb0> no
<lkcl> cr1901_modern: it's a long story, the extension to RISC-V that i've created issues multiple-instructions-for-one
<lkcl> with sequentially-incrementing register numbers being the key augmentation
<lkcl> and the simplest matching microarchitecture is a multi-issue one
<lkcl> certainly not a SIMD one
<lkcl> so i'm interested in the tomasulo algorithm not because of the OoO capability but because you can drop 4+ instructions into the queue on every cycle
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<sb0> lkcl: OOO on FPGA is somewhat tricky, check out https://github.com/terpstra/opa
<lkcl> sb0: thx
<lkcl> sb0: this seems to be an extremely well-known algorithm, that's had a lot of people implement it: https://en.wikipedia.org/wiki/Tomasulo_algorithm
<lkcl> variants include a "reorder buffer" which is basically a copy of the instruction queue with "unfinished" work in it
<lkcl> the instructions may be "worked on" out-of-order
<lkcl> however they must be *committed* in-order.
<lkcl> the scheme also inherently avoids WAR and WAW hazards
<lkcl> because register "names" are actually no longer involved, they're *replaced* with "reservations".
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<GitHub-m-labs> [artiq] KaifengC commented on pull request #1204 f23536c: > On Linux, the `select` call waits for ENTER, and `sys.stdin.read` also waits for ENTER.... https://github.com/m-labs/artiq/pull/1204#discussion_r238269840
<GitHub-m-labs> [artiq] sbourdeauducq commented on pull request #1204 f23536c: ``select`` does not consume any characters, it only checks if something can be read.... https://github.com/m-labs/artiq/pull/1204#discussion_r238270193
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<GitHub-m-labs> [artiq] sbourdeauducq commented on pull request #1204 a817698: Nope. This one will block. You need to call kbhit and then getch. https://github.com/m-labs/artiq/pull/1204#discussion_r238308505
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<GitHub-m-labs> [artiq] drewrisinger commented on issue #1203: > > Changing this will require some refactoring, because `exec_module()` doesn't have any return statement.... https://github.com/m-labs/artiq/issues/1203#issuecomment-443779114
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1203: > why you would want to locate the new module... https://github.com/m-labs/artiq/issues/1203#issuecomment-443792123
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<key2> hi
<key2> has anyone worked on uploading firmwares to misoc using xmodem or something alike ?
<sb0> key2: why xmodem and not the flterm protocol?
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