<GitHub-m-labs>
[artiq] sbourdeauducq commented on pull request #1204 f23536c: Then the behavior is incorrect. You may want to call ``msvcrt.getch`` on Windows instead (and test for the ENTER key so it's consistent with Linux). https://github.com/m-labs/artiq/pull/1204#discussion_r238179602
<lkcl>
there's concepts that are missing in my tiny brain that i need to get up to speed on
<lkcl>
ahh awesome
<lkcl>
whitequark, that's a pretty damn efficient use of 16-bit opcode space
<lkcl>
sort-of huffman encoding
<whitequark>
lkcl: yeah, I spent quite a while on it
<whitequark>
it is also optimized for decoding with LUTs
<lkcl>
the field lines are regularly spaced, R-rst alwys in the same place R-opa linewise
<lkcl>
did you get to the execution unit yet?
<whitequark>
I haven't even started gateware for v2
<whitequark>
but it'll be FSM-driven
<whitequark>
so, effectively microcoded
<lkcl>
oo nice
<whitequark>
it uses only single port RAM, too
<whitequark>
so you could use 256 kB of SPRAM on iCE40UP5K
<lkcl>
*sigh* analysing the requirements for the libre-riscv soc i have this scary feeling i'm going to need to implement the tomasulo algorithm with reorder buffers and everything...
<sb0>
lkcl: look at minerva
<lkcl>
sb0: ahh awesome
<lkcl>
sb0: whereabouts? google searches don't find it
<cr1901_modern>
wait is minerva an out of order core?
<sb0>
o
<sb0>
no
<lkcl>
cr1901_modern: it's a long story, the extension to RISC-V that i've created issues multiple-instructions-for-one
<lkcl>
with sequentially-incrementing register numbers being the key augmentation
<lkcl>
and the simplest matching microarchitecture is a multi-issue one
<lkcl>
certainly not a SIMD one
<lkcl>
so i'm interested in the tomasulo algorithm not because of the OoO capability but because you can drop 4+ instructions into the queue on every cycle