sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
<bb-m-labs> build #2140 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2140
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<bb-m-labs> build #968 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/968
<bb-m-labs> build #2761 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2761
<bb-m-labs> build #2141 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2141
<bb-m-labs> build #2142 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2142
<bb-m-labs> build #969 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/969
<bb-m-labs> build #2762 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2762
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+4/-0/±7] https://git.io/fpdlE
<_whitenotifier> [m-labs/nmigen] whitequark e45e7f1 - Measure test coverage.
<_whitenotifier> [m-labs/nmigen] whitequark dc486ad - fhdl.ast: add tests for most logic.
<_whitenotifier> [m-labs/nmigen] whitequark f0f4c0c - fhdl.ast: bits_sign→shape.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±5] https://git.io/fpdla
<_whitenotifier> [m-labs/nmigen] whitequark 1776764 - tracer: add support for Python 3.7.
<_whitenotifier> [m-labs/nmigen] whitequark b42620e - back.rtlil: match shape of $mux ports A/B/Y.
<_whitenotifier> [m-labs/nmigen] whitequark 22c76e5 - compat.fhdl.module: implement finalization.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fpdlo
<_whitenotifier> [m-labs/nmigen] whitequark a17a9e3 - back.rtlil: give clocks and resets nicer names.
<_whitenotifier> [m-labs/nmigen] whitequark bfd0011 - fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±3] https://git.io/fpd8e
<_whitenotifier> [m-labs/nmigen] whitequark f86ec1e - back.rtlil: explain how RTLIL conversion works.
<_whitenotifier> [m-labs/nmigen] whitequark 4df5c5d - fhdl.ir: explain how port enumeration works.
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<whitequark> sb0: rjo: https://paste.gnome.org/pot6y5bt0
<whitequark> this is BonelessCPU with `from nmigen.compat import *` and the FSM removed
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±3] https://git.io/fpd8Z
<_whitenotifier> [m-labs/nmigen] whitequark 2c67a62 - back.rtlil: explicitly set the top module.
<_whitenotifier> [m-labs/nmigen] whitequark 6c7f98e - back.rtlil: explain logic for CD reset insertion.
<_whitenotifier> [m-labs/nmigen] whitequark 27d3dfc - back.rtlil: fix swapped operands in sync assign.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fpd8l
<_whitenotifier> [m-labs/nmigen] whitequark 4e32f6b - back.verilog: detect undriven public wires using Yosys.
<_whitenotifier> [m-labs/nmigen] whitequark 5b87080 - fhdl.ast: fix Switch._?hs_signals() for switch without statements.
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<whitequark> rjo: ping
<rjo> whitequark: pong
<rjo> whitequark: good and compact. i have a hard time reading that code but can't put my finger on the reason. is the nmigen source in current glasgow (modulo fsm)?
<rjo> maybe its just the wire/reg names and not knowing that cpu.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+2/-1/±5] https://git.io/fpd4v
<_whitenotifier> [m-labs/nmigen] whitequark f70ae3b - fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
<_whitenotifier> [m-labs/nmigen] whitequark 932f191 - fhdl.dsl: use less error-prone Switch/Case two-level syntax.
<whitequark> rjo: yes. current glasgow.
<whitequark> rjo: bikeshed: names of signals in ClockDomain().
<whitequark> in migen it was clk/rst.
<whitequark> but ResetInserter would add a signal named reset.
<whitequark> this always annoyed me.
<whitequark> should we: (a) name then clk/reset and have ResetInserter insert "reset" / "domain_reset"
<whitequark> (b) name them clock/reset and [same]
<whitequark> (c) name them clk/rst and have ResetInserter insert "rst" / "domain_rst"
<whitequark> I've implemented (a) currently.
<whitequark> not sure if (c) is better.
<whitequark> rjo: (re cpu) the CPU arch is fairly well documented: https://github.com/whitequark/Glasgow/blob/master/software/glasgow/arch/boneless/__init__.py
<whitequark> (more re cpu) i've put quite a bit of work into optimizing it. it takes about 500 4-LUT/FFs. might be useful in misoc or even artiq control plane as a dumb sequencer.
<whitequark> the idea is that you program it directly with Python method calls: https://github.com/whitequark/Glasgow/blob/master/software/glasgow/arch/boneless/instr.py
<rjo> on the bikeshedding: i'd prefer abbreviated clk/rst or long clock/reset for the base signals. with ResetInserter, what's supposed to happen if I transform it twice? two additional resets?
<whitequark> yes.
<rjo> how are they named then? what about rst, rst1, rst2 etc?
<whitequark> they... oh I just realized
<whitequark> since nmigen does not generally create attributes anywhere on its own anymore, ResetInserter doesn't do that either
<whitequark> and so it does not come up with names.
<whitequark> you just give it a signal.
<whitequark> which IMO is a much cleaner design.
<rjo> if they become unpredictable, maybe my_reset_signal = AddReset(Domain())
<rjo> exactly.
<whitequark> pix_rst = Signal(); ResetInserter({"pix": pix_rst})(f)
<rjo> yes. nice.
<whitequark> ok, clk/rst it is.
<rjo> do we actually want to transform fragments/modules or rather domains (and then ReplaceDomain("sync": DomainWithReset()}, f))
<whitequark> I think we want to transform modules.
<rjo> i tend to agree.
<whitequark> domains are fairly heavyweight in migen/nmigen
<whitequark> they're global, and the propagation is fairly implicit.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±6] https://git.io/fpd4I
<_whitenotifier> [m-labs/nmigen] whitequark e0a81ed - fhdl.dsl: add tests for submodules.
<_whitenotifier> [m-labs/nmigen] whitequark d2e2d00 - fhdl.cd: rename ClockDomain.{reset→rst}.
<_whitenotifier> [m-labs/nmigen] whitequark a797e27 - fhdl.dsl: add tests for lowering. 99% branch coverage.
<rjo> _whitenotifier: what python version is that supposed to be? with 3.5 i get an encoding=... error in verilog output, with 3.6 it's bytes vs str, with 2.7 it's no builtins module.
<rjo> whitequark: ^
<whitequark> rjo: i use 3.7 :D
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpd4m
<_whitenotifier> [m-labs/nmigen] whitequark 48330f8 - setup: check Python version.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+2/-0/±0] https://git.io/fpd4O
<_whitenotifier> [m-labs/nmigen] whitequark 1f1aa7f - Add LICENSE.
<_whitenotifier> [m-labs/nmigen] whitequark dc8b5ef - Set up Travis CI.
<_whitenotifier> [nmigen] Pending. The Travis CI build is in progress - https://travis-ci.org/m-labs/nmigen/builds/467381904?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Pending. The Travis CI build is in progress - https://travis-ci.org/m-labs/nmigen/builds/467381904?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/467381904?utm_source=github_status&utm_medium=notification
<whitequark> ... Travis doesn't have 3.7?
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±0] https://git.io/fpd43
<_whitenotifier> [m-labs/nmigen] whitequark c603925 - Set up Travis CI.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467382355?utm_source=github_status&utm_medium=notification
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±2] https://git.io/fpd48
<_whitenotifier> [m-labs/nmigen] whitequark b1a89ef - fhdl.ir: add tests for port propagation.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467387481?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 72.28% (+2.3%) compared to c603925 - https://codecov.io/gh/m-labs/nmigen/commit/b1a89ef5fd86a149a5afa946899726c0d843f269
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 69.97%) - https://codecov.io/gh/m-labs/nmigen/commit/b1a89ef5fd86a149a5afa946899726c0d843f269
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±1] https://git.io/fpd4S
<_whitenotifier> [m-labs/nmigen] whitequark 19aa404 - fhdl.xfrm: add tests for ResetInserter, CEInserter.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467397160?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 74.25% (+1.96%) compared to b1a89ef - https://codecov.io/gh/m-labs/nmigen/commit/19aa40462822f5eec6620778a32a90d1c9553356
<_whitenotifier> [nmigen] Success. 92.59% of diff hit (target 72.28%) - https://codecov.io/gh/m-labs/nmigen/commit/19aa40462822f5eec6620778a32a90d1c9553356
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+2/-1/±5] https://git.io/fpdBY
<_whitenotifier> [m-labs/nmigen] whitequark 8963ab5 - fhdl.xfrm: add test for ControlInserter with subfragments.
<_whitenotifier> [m-labs/nmigen] whitequark 9bee90f - fhdl.xfrm: implement DomainRenamer.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467402963?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 76.28% (+2.03%) compared to 19aa404 - https://codecov.io/gh/m-labs/nmigen/commit/9bee90f1bdce3498105a31ce3b2abb90311af089
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 74.25%) - https://codecov.io/gh/m-labs/nmigen/commit/9bee90f1bdce3498105a31ce3b2abb90311af089
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+1/-0/±10] https://git.io/fpdRw
<_whitenotifier> [m-labs/nmigen] whitequark c5087ed - fhdl.cd: add tests.
<_whitenotifier> [m-labs/nmigen] whitequark f4340c1 - fhdl: cd_name→domain.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467431064?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 76.19% of diff hit (target 76.28%) - https://codecov.io/gh/m-labs/nmigen/commit/f4340c19bb38e2db96ccbee10416154e963a1b4f
<_whitenotifier> [nmigen] Success. 77.47% (+1.18%) compared to 9bee90f - https://codecov.io/gh/m-labs/nmigen/commit/f4340c19bb38e2db96ccbee10416154e963a1b4f
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±15] https://git.io/fpd0o
<_whitenotifier> [m-labs/nmigen] whitequark fde2471 - fhdl.ir: remove iter_domains().
<_whitenotifier> [m-labs/nmigen] whitequark 72257b6 - fhdl.ir: implement clock domain propagation.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467447933?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 79.81% (+2.33%) compared to f4340c1 - https://codecov.io/gh/m-labs/nmigen/commit/72257b6935c6b5df4f85d350335ce64ab1701f76
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 77.47%) - https://codecov.io/gh/m-labs/nmigen/commit/72257b6935c6b5df4f85d350335ce64ab1701f76
<whitequark> rjo: sneak peek: https://paste.gnome.org/phhtupk9h
<whitequark> cc sb0
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±8] https://git.io/fpdET
<_whitenotifier> [m-labs/nmigen] whitequark b150f19 - fhdl.ir: don't crash propagataing ports in empty fragments.
<_whitenotifier> [m-labs/nmigen] whitequark 859c2db - back.rtlil: never give subfragment cells names starting with $.
<_whitenotifier> [m-labs/nmigen] whitequark bb04c9e - fhdl, back: trace and emit source locations of values.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467465538?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 79.78% (-0.04%) compared to 72257b6 - https://codecov.io/gh/m-labs/nmigen/commit/bb04c9e0dac4d9ae211b4c9392ef01a4ec69e88a
<_whitenotifier> [nmigen] Failure. 72.41% of diff hit (target 79.81%) - https://codecov.io/gh/m-labs/nmigen/commit/bb04c9e0dac4d9ae211b4c9392ef01a4ec69e88a
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fpdEI
<_whitenotifier> [m-labs/nmigen] whitequark 9661e89 - fhdl.ir: a subfragment's input that we don't drive is also our input.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467467098?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 79.79% (+0.01%) compared to bb04c9e - https://codecov.io/gh/m-labs/nmigen/commit/9661e897e651ba13d1107db7d9bc4521cf3c71fc
<_whitenotifier> [nmigen] Success. 100% of diff hit (target 79.78%) - https://codecov.io/gh/m-labs/nmigen/commit/9661e897e651ba13d1107db7d9bc4521cf3c71fc
<whitequark> the old migen fsm is really impressive
<whitequark> in the sense of (amount of mess) / (lines of code)
<whitequark> it's like it's trying to reimplement half of migen, poorly
<whitequark> the more i look at it, the less convinced i am that i understand its semantics at all
<whitequark> just... going to put it as-is, i guess
<cr1901_modern> Oh cool, you added codecov.io to the notifier :D
<whitequark> it does that by itself
<cr1901_modern> Oh, interesting
<cr1901_modern> is codecov sending data to Github which notifico then receives?
<whitequark> sb0: rjo: I've successfully synthesized BonelessCPU with nmigen!
<whitequark> in compat mode.
<whitequark> by "successfully" I mean "yosys stopped removing all the logic"
<whitequark> not sure if it simulates yet.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+1/-0/±8] https://git.io/fpduV
<_whitenotifier> [m-labs/nmigen] whitequark 6251c95 - compat.genlib.fsm: import/wrap Migen code.
<_whitenotifier> [m-labs/nmigen] whitequark 90f1503 - fhdl.ir: record port direction explicitly.
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<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467499837?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 71.98% (-7.82%) compared to 9661e89 - https://codecov.io/gh/m-labs/nmigen/commit/90f1503c918ccf5d7645f126cb03dc05dce47b00
<_whitenotifier> [nmigen] Failure. 54.16% of diff hit (target 79.79%) - https://codecov.io/gh/m-labs/nmigen/commit/90f1503c918ccf5d7645f126cb03dc05dce47b00
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±5] https://git.io/fpdzd
<_whitenotifier> [m-labs/nmigen] whitequark ac49841 - back.verilog: remove debug code.
<_whitenotifier> [m-labs/nmigen] whitequark 424c5b3 - fhdl.ir: move Fragment prepare logic from back.rtlil.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±4] https://git.io/fpdzF
<_whitenotifier> [m-labs/nmigen] whitequark 07c818e - fhdl.ir: move Fragment prepare logic from back.rtlil.
<_whitenotifier> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/467534548?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467534794?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 71.29% (-0.7%) compared to 90f1503 - https://codecov.io/gh/m-labs/nmigen/commit/07c818e077d1588d70356c78cd2d241dcc931008
<_whitenotifier> [nmigen] Failure. 26.31% of diff hit (target 71.98%) - https://codecov.io/gh/m-labs/nmigen/commit/07c818e077d1588d70356c78cd2d241dcc931008
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<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fpdg7
<_whitenotifier> [m-labs/nmigen] whitequark 71f1f71 - fhdl.cd: rename ClockDomain signals together with domain.
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467559933?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 71.41% (+0.12%) compared to 07c818e - https://codecov.io/gh/m-labs/nmigen/commit/71f1f717c47f193d14cc7285632b7c88314f5a7b
<_whitenotifier> [nmigen] Success. 91.66% of diff hit (target 71.29%) - https://codecov.io/gh/m-labs/nmigen/commit/71f1f717c47f193d14cc7285632b7c88314f5a7b
<sb0> what is the actual minimum TTL pulse rate on the EEM cards?
<sb0> the wiki says 3ns, the isolator chip datasheet says 5ns
<sb0> *pulse width
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<whitequark> sb0: rjo: https://imgur.com/a/yL83FJD
<whitequark> this is a true event-driven simulator with delta cycles that JIT-compiles nMigen expressions to Python
<whitequark> still kind of slow though
<_whitenotifier> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±8] https://git.io/fpdVh
<_whitenotifier> [m-labs/nmigen] whitequark fb27c25 - back.pysim: new simulator backend (WIP).
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467635002?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Failure. 71% (-0.41%) compared to 71f1f71 - https://codecov.io/gh/m-labs/nmigen/commit/fb27c2520b55b9bdf42d2cd81580da534a74f2db
<_whitenotifier> [nmigen] Failure. 52% of diff hit (target 71.41%) - https://codecov.io/gh/m-labs/nmigen/commit/fb27c2520b55b9bdf42d2cd81580da534a74f2db
<sb0> whitequark: what do you need the event-driven aspect for?
<sb0> whitequark: if there are no true comb loops, you could reorganize the comb statements instead, and run it only once at every clock cycles
<whitequark> sb0: seems less error-prone to do it this way
<whitequark> or at least, it is easier to convince myself that it works correctly
<whitequark> also, this way, it would naturally handle async resets
<whitequark> migen.sim doesn't even handle AsyncResetSynchronizer, it's a TODO.
<whitequark> your point about not handling async resets directly seems moot if you don't handle them as special cases either.
<_whitenotifier> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±4] https://git.io/fpdoJ
<_whitenotifier> [m-labs/nmigen] whitequark 6a4004e - back.pysim: fix handling of process termination.
<_whitenotifier> [m-labs/nmigen] whitequark a7ebc02 - back.pysim: allow multiple registered handlers per signal.
<_whitenotifier> [m-labs/nmigen] whitequark b09f4b1 - back.pysim: collect handlers before running (-5% runtime).
<_whitenotifier> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/467647491?utm_source=github_status&utm_medium=notification
<_whitenotifier> [nmigen] Success. 71% remains the same compared to fb27c25 - https://codecov.io/gh/m-labs/nmigen/commit/b09f4b10ee681808a7ae1b16084a7b04636bdf2c
<_whitenotifier> [nmigen] Success. Coverage not affected when comparing fb27c25...b09f4b1 - https://codecov.io/gh/m-labs/nmigen/commit/b09f4b10ee681808a7ae1b16084a7b04636bdf2c
<sb0> whitequark: btw Olof on twitter suggested using edalize for the build system
<sb0> oh and with this ECP5 and yosys, maybe we can compile parts of ARTIQ-Python into the FPGA fabric, for super-low latency
<sb0> does the ECP5 play nice with partial reconfiguration?
<_whitenotifier> [nmigen] mithro opened issue #1: Example of embedding exisiting Verilog? - https://git.io/fpdHW
<GitHub-m-labs> [artiq] jbqubit commented on issue #1124: Agreed. Postpone investigation until Sayma v2 hardware is available. https://github.com/m-labs/artiq/issues/1124#issuecomment-447128935
<_whitenotifier> [nmigen] jordens commented on issue #1: Example of embedding exisiting Verilog? - https://git.io/fpdFw
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<daveshah> sb0: unfortunately as far as I can see partial reconfig isn't possible on the ecp5
<daveshah> It's not officially supported and it uses fairly large config frames each with a bit of everything in them so hacking it isn't possible either
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<mithro> _whitenotifier: you own _whitenotifier and _whitenotifier right?
<mithro> whitequark: Would you add the #symbiflow channel to _whitelogger and maybe setup SymbiFlow repos to notify open issues to the #symbiflow channel?