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_whitenotifier >
[m-labs/nmigen] whitequark e45e7f1 - Measure test coverage.
02:08
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_whitenotifier >
[m-labs/nmigen] whitequark dc486ad - fhdl.ast: add tests for most logic.
02:08
<
_whitenotifier >
[m-labs/nmigen] whitequark f0f4c0c - fhdl.ast: bits_sign→shape.
02:36
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_whitenotifier >
[m-labs/nmigen] whitequark 1776764 - tracer: add support for Python 3.7.
02:36
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_whitenotifier >
[m-labs/nmigen] whitequark b42620e - back.rtlil: match shape of $mux ports A/B/Y.
02:36
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_whitenotifier >
[m-labs/nmigen] whitequark 22c76e5 - compat.fhdl.module: implement finalization.
02:43
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_whitenotifier >
[m-labs/nmigen] whitequark a17a9e3 - back.rtlil: give clocks and resets nicer names.
02:43
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_whitenotifier >
[m-labs/nmigen] whitequark bfd0011 - fhdl.ir: make sure clocks and resets of used CDs appear as inputs.
03:28
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_whitenotifier >
[m-labs/nmigen] whitequark f86ec1e - back.rtlil: explain how RTLIL conversion works.
03:31
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_whitenotifier >
[m-labs/nmigen] whitequark 4df5c5d - fhdl.ir: explain how port enumeration works.
03:42
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whitequark >
this is BonelessCPU with `from nmigen.compat import *` and the FSM removed
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_whitenotifier >
[m-labs/nmigen] whitequark 2c67a62 - back.rtlil: explicitly set the top module.
04:45
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_whitenotifier >
[m-labs/nmigen] whitequark 6c7f98e - back.rtlil: explain logic for CD reset insertion.
04:46
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_whitenotifier >
[m-labs/nmigen] whitequark 27d3dfc - back.rtlil: fix swapped operands in sync assign.
05:00
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_whitenotifier >
[m-labs/nmigen] whitequark 4e32f6b - back.verilog: detect undriven public wires using Yosys.
05:00
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_whitenotifier >
[m-labs/nmigen] whitequark 5b87080 - fhdl.ast: fix Switch._?hs_signals() for switch without statements.
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06:10
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whitequark >
rjo: ping
06:45
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rjo >
whitequark: pong
06:51
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rjo >
whitequark: good and compact. i have a hard time reading that code but can't put my finger on the reason. is the nmigen source in current glasgow (modulo fsm)?
06:58
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rjo >
maybe its just the wire/reg names and not knowing that cpu.
07:11
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_whitenotifier >
[m-labs/nmigen] whitequark f70ae3b - fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
07:11
<
_whitenotifier >
[m-labs/nmigen] whitequark 932f191 - fhdl.dsl: use less error-prone Switch/Case two-level syntax.
07:11
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whitequark >
rjo: yes. current glasgow.
07:12
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whitequark >
rjo: bikeshed: names of signals in ClockDomain().
07:12
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whitequark >
in migen it was clk/rst.
07:12
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whitequark >
but ResetInserter would add a signal named reset.
07:12
<
whitequark >
this always annoyed me.
07:12
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whitequark >
should we: (a) name then clk/reset and have ResetInserter insert "reset" / "domain_reset"
07:13
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whitequark >
(b) name them clock/reset and [same]
07:13
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whitequark >
(c) name them clk/rst and have ResetInserter insert "rst" / "domain_rst"
07:13
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whitequark >
I've implemented (a) currently.
07:13
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whitequark >
not sure if (c) is better.
07:14
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whitequark >
(more re cpu) i've put quite a bit of work into optimizing it. it takes about 500 4-LUT/FFs. might be useful in misoc or even artiq control plane as a dumb sequencer.
07:20
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rjo >
on the bikeshedding: i'd prefer abbreviated clk/rst or long clock/reset for the base signals. with ResetInserter, what's supposed to happen if I transform it twice? two additional resets?
07:21
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rjo >
how are they named then? what about rst, rst1, rst2 etc?
07:22
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whitequark >
they... oh I just realized
07:22
<
whitequark >
since nmigen does not generally create attributes anywhere on its own anymore, ResetInserter doesn't do that either
07:22
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whitequark >
and so it does not come up with names.
07:22
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whitequark >
you just give it a signal.
07:22
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whitequark >
which IMO is a much cleaner design.
07:22
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rjo >
if they become unpredictable, maybe my_reset_signal = AddReset(Domain())
07:23
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whitequark >
pix_rst = Signal(); ResetInserter({"pix": pix_rst})(f)
07:24
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whitequark >
ok, clk/rst it is.
07:24
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rjo >
do we actually want to transform fragments/modules or rather domains (and then ReplaceDomain("sync": DomainWithReset()}, f))
07:24
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whitequark >
I think we want to transform modules.
07:25
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rjo >
i tend to agree.
07:25
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whitequark >
domains are fairly heavyweight in migen/nmigen
07:25
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whitequark >
they're global, and the propagation is fairly implicit.
07:34
<
_whitenotifier >
[m-labs/nmigen] whitequark e0a81ed - fhdl.dsl: add tests for submodules.
07:34
<
_whitenotifier >
[m-labs/nmigen] whitequark d2e2d00 - fhdl.cd: rename ClockDomain.{reset→rst}.
07:34
<
_whitenotifier >
[m-labs/nmigen] whitequark a797e27 - fhdl.dsl: add tests for lowering. 99% branch coverage.
07:42
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rjo >
_whitenotifier: what python version is that supposed to be? with 3.5 i get an encoding=... error in verilog output, with 3.6 it's bytes vs str, with 2.7 it's no builtins module.
07:42
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rjo >
whitequark: ^
07:45
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whitequark >
rjo: i use 3.7 :D
07:47
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_whitenotifier >
[m-labs/nmigen] whitequark 48330f8 - setup: check Python version.
07:52
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_whitenotifier >
[m-labs/nmigen] whitequark 1f1aa7f - Add LICENSE.
07:52
<
_whitenotifier >
[m-labs/nmigen] whitequark dc8b5ef - Set up Travis CI.
07:53
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whitequark >
... Travis doesn't have 3.7?
07:54
<
_whitenotifier >
[m-labs/nmigen] whitequark c603925 - Set up Travis CI.
08:09
<
_whitenotifier >
[m-labs/nmigen] whitequark b1a89ef - fhdl.ir: add tests for port propagation.
08:39
<
_whitenotifier >
[m-labs/nmigen] whitequark 19aa404 - fhdl.xfrm: add tests for ResetInserter, CEInserter.
08:47
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08:57
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_whitenotifier >
[m-labs/nmigen] whitequark 8963ab5 - fhdl.xfrm: add test for ControlInserter with subfragments.
08:57
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_whitenotifier >
[m-labs/nmigen] whitequark 9bee90f - fhdl.xfrm: implement DomainRenamer.
10:15
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_whitenotifier >
[m-labs/nmigen] whitequark c5087ed - fhdl.cd: add tests.
10:15
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_whitenotifier >
[m-labs/nmigen] whitequark f4340c1 - fhdl: cd_name→domain.
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11:01
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_whitenotifier >
[m-labs/nmigen] whitequark fde2471 - fhdl.ir: remove iter_domains().
11:01
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_whitenotifier >
[m-labs/nmigen] whitequark 72257b6 - fhdl.ir: implement clock domain propagation.
11:35
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whitequark >
cc sb0
11:47
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_whitenotifier >
[m-labs/nmigen] whitequark b150f19 - fhdl.ir: don't crash propagataing ports in empty fragments.
11:47
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_whitenotifier >
[m-labs/nmigen] whitequark 859c2db - back.rtlil: never give subfragment cells names starting with $.
11:47
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_whitenotifier >
[m-labs/nmigen] whitequark bb04c9e - fhdl, back: trace and emit source locations of values.
11:51
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_whitenotifier >
[m-labs/nmigen] whitequark 9661e89 - fhdl.ir: a subfragment's input that we don't drive is also our input.
11:53
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whitequark >
the old migen fsm is really impressive
11:53
<
whitequark >
in the sense of (amount of mess) / (lines of code)
11:54
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whitequark >
it's like it's trying to reimplement half of migen, poorly
11:57
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whitequark >
the more i look at it, the less convinced i am that i understand its semantics at all
12:11
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whitequark >
just... going to put it as-is, i guess
12:44
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cr1901_modern >
Oh cool, you added codecov.io to the notifier :D
12:49
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whitequark >
it does that by itself
12:53
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cr1901_modern >
Oh, interesting
13:06
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cr1901_modern >
is codecov sending data to Github which notifico then receives?
13:06
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whitequark >
sb0: rjo: I've successfully synthesized BonelessCPU with nmigen!
13:06
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whitequark >
in compat mode.
13:06
<
whitequark >
by "successfully" I mean "yosys stopped removing all the logic"
13:06
<
whitequark >
not sure if it simulates yet.
13:18
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_whitenotifier >
[m-labs/nmigen] whitequark 6251c95 - compat.genlib.fsm: import/wrap Migen code.
13:18
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_whitenotifier >
[m-labs/nmigen] whitequark 90f1503 - fhdl.ir: record port direction explicitly.
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14:33
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_whitenotifier >
[m-labs/nmigen] whitequark ac49841 - back.verilog: remove debug code.
14:33
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_whitenotifier >
[m-labs/nmigen] whitequark 424c5b3 - fhdl.ir: move Fragment prepare logic from back.rtlil.
14:34
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_whitenotifier >
[m-labs/nmigen] whitequark 07c818e - fhdl.ir: move Fragment prepare logic from back.rtlil.
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_whitenotifier >
[m-labs/nmigen] whitequark 71f1f71 - fhdl.cd: rename ClockDomain signals together with domain.
15:34
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sb0 >
what is the actual minimum TTL pulse rate on the EEM cards?
15:35
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sb0 >
the wiki says 3ns, the isolator chip datasheet says 5ns
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17:21
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whitequark >
this is a true event-driven simulator with delta cycles that JIT-compiles nMigen expressions to Python
17:25
<
whitequark >
still kind of slow though
18:02
<
_whitenotifier >
[m-labs/nmigen] whitequark fb27c25 - back.pysim: new simulator backend (WIP).
18:19
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sb0 >
whitequark: what do you need the event-driven aspect for?
18:19
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sb0 >
whitequark: if there are no true comb loops, you could reorganize the comb statements instead, and run it only once at every clock cycles
18:20
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whitequark >
sb0: seems less error-prone to do it this way
18:20
<
whitequark >
or at least, it is easier to convince myself that it works correctly
18:21
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whitequark >
also, this way, it would naturally handle async resets
18:21
<
whitequark >
migen.sim doesn't even handle AsyncResetSynchronizer, it's a TODO.
18:21
<
whitequark >
your point about not handling async resets directly seems moot if you don't handle them as special cases either.
18:35
<
_whitenotifier >
[m-labs/nmigen] whitequark 6a4004e - back.pysim: fix handling of process termination.
18:35
<
_whitenotifier >
[m-labs/nmigen] whitequark a7ebc02 - back.pysim: allow multiple registered handlers per signal.
18:35
<
_whitenotifier >
[m-labs/nmigen] whitequark b09f4b1 - back.pysim: collect handlers before running (-5% runtime).
18:56
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sb0 >
whitequark: btw Olof on twitter suggested using edalize for the build system
18:58
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sb0 >
oh and with this ECP5 and yosys, maybe we can compile parts of ARTIQ-Python into the FPGA fabric, for super-low latency
18:58
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sb0 >
does the ECP5 play nice with partial reconfiguration?
21:37
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_whitenotifier >
[nmigen] jordens commented on issue #1: Example of embedding exisiting Verilog? -
https://git.io/fpdFw
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daveshah >
sb0: unfortunately as far as I can see partial reconfig isn't possible on the ecp5
22:13
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daveshah >
It's not officially supported and it uses fairly large config frames each with a bit of everything in them so hacking it isn't possible either
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23:05
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mithro >
_whitenotifier: you own _whitenotifier and _whitenotifier right?
23:11
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mithro >
whitequark: Would you add the #symbiflow channel to _whitelogger and maybe setup SymbiFlow repos to notify open issues to the #symbiflow channel?