sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark: arguably not the same problem, since you could stop and think whether the number you are shifting (1) is a 32- or 64-bit integer. but the compiler had no reason at all to make the large constant 32-bit.
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<whitequark> yes. i agree the issue i just fixed was a compiler bug. i haven't noticed that it is.
<_whitenotifier-e> [nmigen] sam-falvo synchronize pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhszI
<kc5tja> Greetings -- hoping someone can please review my PR, in particular the Memories section? I've marked two spots in particular which I need clarification on.
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478922970?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.53% remains the same compared to 560bb00 - https://codecov.io/gh/m-labs/nmigen/compare/560bb007cc3c7e5921ac353311dddb49f5da180e...5f7a18390c7d5911f93952fce1336da9004c4f23
<_whitenotifier-e> [nmigen] Success. Coverage not affected when comparing 560bb00...5f7a183 - https://codecov.io/gh/m-labs/nmigen/compare/560bb007cc3c7e5921ac353311dddb49f5da180e...5f7a18390c7d5911f93952fce1336da9004c4f23
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<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhnaD
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhnaS
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhna9
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhnaQ
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhna7
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhna5
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhnad
<bb-m-labs> build #2247 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2247
<_whitenotifier-e> [nmigen] whitequark reviewed pull request #22 commit - https://git.io/fhnab
<bb-m-labs> build #2248 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2248
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<kc5tja> whitequark: I think you reviewed text which was from the legacy documentation. I hadn't finished all of hdl.rst yet. :P But, the input is valuable.
<whitequark> kc5tja: ah, okay!
<kc5tja> Regarding transparent terminology, this use of the term is new to me. When I searched for transparent RAM online, everything I found was about transparent latches. It makes sense; I just remember seeing a different term is all. It helps explain a lot though. Thank you for the feedback.
<whitequark> you might find the Yosys manual helpful
<whitequark> it is not required, but as nMigen in many ways borrows from Yosys, it may be helpful
<kc5tja> Sorry it's taking as long as it is. I get only a few hours on weekends, and I'm still learning nMigen as well.
<kc5tja> Awesome, thanks. I'll add that to my consulting/reference documents list.
<whitequark> it's fine. there is no particular rush
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<sb0> whitequark: as for rust kernels, they could potentially exist alongside the existing ones. the questions are, who will use it, who will fund it, and who will implement and maintain it.
<whitequark> sb0: what i am saying is, i can maintain the existing ARTIQ Python compiler. i can make its semantics less bad. but i cannot fix things that are bad because of fundamental properties of the semantics we chose
<whitequark> the closest thing to fixing integer literals would be to enable overflow checking on mor1kx
<sb0> fixing what exactly?
<whitequark> fixing the fact that they will silently overflow with no tools that could show that
<whitequark> ubsan shows that both signed and unsigned overflows are rarely desired outside of certain classes of programs, like cryptographic algorithms
<sb0> or phase computations...
<whitequark> sure
<whitequark> or well, we don't even have to go to ubsan, rust panics on overflow
<sb0> what is the best option in your opinion? regular integers throw an exception on overflow, and add another type for power-of-two modular arithmetic that disables the exception?
<_whitenotifier-e> [nmigen] sam-falvo synchronize pull request #22: Updated user guide introduction for nmigen. - https://git.io/fhszI
<whitequark> I think adding another type would work rather poorly with our inference and Python's implicit conversion rules
<whitequark> I think the two options that would work best are either a) methods like .overflowing_add() a la rust
<whitequark> b) `with overflow:`
<whitequark> probably b) is more pythonic
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478935731?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.53% remains the same compared to 560bb00 - https://codecov.io/gh/m-labs/nmigen/compare/560bb007cc3c7e5921ac353311dddb49f5da180e...1bf4f28de79ae731e507553e6b7439e702aff93e
<_whitenotifier-e> [nmigen] Success. Coverage not affected when comparing 560bb00...1bf4f28 - https://codecov.io/gh/m-labs/nmigen/compare/560bb007cc3c7e5921ac353311dddb49f5da180e...1bf4f28de79ae731e507553e6b7439e702aff93e
<kc5tja> whitequark: I seem to recall from a previous discussion here that specials are not supported in nMigen. Am I remembering correctly? There are no examples making use of specials that I can find.
<whitequark> there are no specials in nMigen
<whitequark> there are only memories and instances, as special cases (but not a specific entity. just special cases in general.P)
<attie> specials were just a workaround for "this needs a description that can't be generated with regular migen code", right?
<kc5tja> Roger that. I'll strip my copy of the docs of specials. I suspect submodules is pretty consistent between Migen and nMigen.
<whitequark> attie: yeah
<whitequark> in migen, everything is a fragment, some fragments are also instances, and some instances are also memories
<whitequark> instances and memories can (and in case of memories, always do) contain behavioral logic for simulation
<whitequark> hmm, adding Tristate with this scheme will probably require native support for 'z
<whitequark> I guess I can do that without ever exposing it to user
<kc5tja> whitequark: Is there a place I can reference to learn how clock domains are used in nMigen? Perhaps an example HDL listing?
<whitequark> not at the moment, but it should be very similar to Migen
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<kc5tja> Forgive me if I'm asking
<kc5tja> oops
<kc5tja> Forgive me if I'm asking repeated questions; I see in Migen, m.sync.<domain> += statements is a valid construct. However, i've not seen a similar construct for nMigen. Unit tests show creation of multiple domains, and adding them to the domains member of a module, but they're never used.
<kc5tja> How would one use these multiple domains?
<whitequark> so let's say you added a domain called foo
<whitequark> you would use it with `m.d.foo +=`
<whitequark> `sync` is just the default domain
<whitequark> (like `sys` was in migen)
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<kc5tja> Ahh, thanks!
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<_whitenotifier-e> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhnw2
<_whitenotifier-e> [m-labs/nmigen] whitequark 06faeee - back.verilog: better error message if Yosys is not found.
<_whitenotifier-e> [nmigen] whitequark closed issue #17: Add a more user-friendly error message when the yosys binary can't be found - https://git.io/fht2R
<_whitenotifier-e> [nmigen] whitequark commented on pull request #19: Fix #17 (Add a more user-friendly error message when the yosys binary can't be found) - https://git.io/fhnwa
<_whitenotifier-e> [nmigen] whitequark closed pull request #19: Fix #17 (Add a more user-friendly error message when the yosys binary can't be found) - https://git.io/fhnwV
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478955970?utm_source=github_status&utm_medium=notification
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<_whitenotifier-e> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fhnwX
<_whitenotifier-e> [m-labs/nmigen] whitequark cbf7bd6 - back.pysim: handle non-driven, non-port signals.
<_whitenotifier-e> [nmigen] whitequark closed issue #20: Memory with only a read port fails in pysim - https://git.io/fh33D
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478959158?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.55% (+0.01%) compared to 06faeee - https://codecov.io/gh/m-labs/nmigen/commit/cbf7bd6e315e52920c98afd72acc05eec8f5f078
<_whitenotifier-e> [nmigen] Success. 100% of diff hit (target 80.53%) - https://codecov.io/gh/m-labs/nmigen/commit/cbf7bd6e315e52920c98afd72acc05eec8f5f078
<_whitenotifier-e> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fhnwA
<_whitenotifier-e> [m-labs/nmigen] whitequark 3083c1d - hdl.dsl: accept (but warn on) cases wider than switch test value.
<_whitenotifier-e> [nmigen] whitequark closed issue #13: Case with key wider than test results in assertion failure - https://git.io/fhJ1S
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478961429?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.6% (+0.04%) compared to cbf7bd6 - https://codecov.io/gh/m-labs/nmigen/commit/3083c1d6ddc2a80b745152eb6ee406d8ed3c5d12
<_whitenotifier-e> [nmigen] Success. 100% of diff hit (target 80.55%) - https://codecov.io/gh/m-labs/nmigen/commit/3083c1d6ddc2a80b745152eb6ee406d8ed3c5d12
<_whitenotifier-e> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fhnrI
<_whitenotifier-e> [m-labs/nmigen] whitequark 664b4bc - hdl.dsl: cases wider than switch test value are unreachable.
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/478962171?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.61% (+0.01%) compared to 3083c1d - https://codecov.io/gh/m-labs/nmigen/commit/664b4bcb3ac2e4c688707677def1cb6b4075ea7b
<_whitenotifier-e> [nmigen] Success. 100% of diff hit (target 80.6%) - https://codecov.io/gh/m-labs/nmigen/commit/664b4bcb3ac2e4c688707677def1cb6b4075ea7b
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhnrm
<whitequark> key2_: ping
<whitequark> you had some FIFO code ported to nmigen, right?
<whitequark> i am interested in that
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<bb-m-labs> build #2822 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2822 blamelist: whitequark <whitequark@whitequark.org>
<sb0> wow, xilinx seems to have fixed a bunch of bugs in the 2018.3 transceiver wizard
<sb0> it's still a shitty GUI, but at least you're not spending most of the time working around blatant bugs
<sb0> (this thing, of course, shouldn't be GUI at all, which would save both developer and user time...)
<sb0> even relatively complicated things like the programmable clock divider seem to work properly
<sb0> the GTH can also do 1:10 without wasting MMCMs/PLLs... probably the only GTH I/O feature that has improved
<sb0> *ultrascale
<bb-m-labs> build #2249 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2249
<sb0> they cleaned up the generated code, too
<sb0> it's still a mess, but it's a smaller mess
<sb0> whitequark: did you look into verilog parsers for python?
<whitequark> did you ask me to?
<sb0> no, just wondering if you happened to come across a good one
<whitequark> nope. what do you want to do?
<whitequark> parse the output of xilinx generator?
<sb0> yes
<whitequark> can you feed it into yosys and output rtlil?
<bb-m-labs> build #2250 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2250
<whitequark> well, you could also tell yosys to print verilog ast
<whitequark> not sure what is easier to make sense of, in that case
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<bb-m-labs> build #2823 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2823 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> pyverilog chokes on the xilinx code, of course
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<bb-m-labs> build #2251 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2251
<bb-m-labs> build #2252 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2252
<bb-m-labs> build #2824 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2824 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<d_n|a> bb-m-labs: force build --branch=pull/1244/head artiq
<bb-m-labs> build forced [ETA 58m23s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #2253 of artiq-board is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2253
<bb-m-labs> build #2825 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2825
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<d_n|a> Huh?
<d_n|a> bb-m-labs: force build --branch=pull/1244/head artiq
<bb-m-labs> build forced [ETA 58m23s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #2254 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2254
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<bb-m-labs> build #2255 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2255
<bb-m-labs> build #2826 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2826
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<d_n|a> Hmm, this seems like slightly weird behaviour ^. Passing self.channel to an int64 parameter apparently makes it be inferred as int64, even though it is assigned an int32. (whitequark: No idea whether that behaviour has only just changed, though.)
<d_n|a> bb-m-labs: force build --branch=pull/1244/merge artiq
<bb-m-labs> build forced [ETA 58m23s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #2256 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2256
<_whitenotifier-e> [nmigen] peteut commented on issue #24: Project Structure And Tox - https://git.io/fhn9G
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<bb-m-labs> build #2257 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2257
<bb-m-labs> build #2827 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2827
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