sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<sb0> jason1: what's on the kc705 uart when it boots?
<sb0> jason1: are all the relevant ethernet link LEDs on?
<GitHub146> [smoltcp] whitequark commented on issue #269: Personally, I would enable the highest log level and then very carefully examine the Wireshark packet traces against the verbose logs. Unfortunately there is no better way applicable in all cases that I'm aware of; TCP stacks are tricky to test automatically. https://github.com/m-labs/smoltcp/issues/269#issuecomment-458375945
<GitHub-m-labs> [artiq] whitequark commented on issue #1255: This is likely because of the serialization code. I think the proper solution is to add fast paths for specific kinds of arrays. https://github.com/m-labs/artiq/issues/1255#issuecomment-458376301
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1162: @whitequark Any update? https://github.com/m-labs/artiq/issues/1162#issuecomment-458376486
<_whitenotifier-c> [nmigen] whitequark commented on issue #32: back.verilog: Memory with asynchronous transparent read port needs a CLK signal ? - https://git.io/fhPNJ
<bb-m-labs> build #1014 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/1014
<bb-m-labs> build #2877 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2877
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/90c9fa446f79...2e8decbce37e
<GitHub-m-labs> artiq/master 2e8decb Sebastien Bourdeauducq: kasli_sawgmaster: generate a HMC830 clock with Urukul
<GitHub-m-labs> artiq/master 9ae57fd Sebastien Bourdeauducq: sayma: pass rtio_clk_freq to DDMTD core
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<sb0> _florent_: how did you determine the SYSREF frequency?
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<bb-m-labs> build #2357 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2357
<sb0> whitequark: why did you choose windows-7 (and not the more recent versions) on the buildbot?
<whitequark> sb0: the other options were 8 and 10
<bb-m-labs> build #2358 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2358
<sb0> and?
<whitequark> at the time 10 was very new, and in retrospect, using any branch of 10 except LTSB is a bad idea
<whitequark> i don't remember what was the issue with 8
<sb0> how do you get past the LTSB activation crap? checkpoint the VM + fake date? or is there a handy crack available?
<whitequark> hm, my LTSB images don't require activation
<whitequark> which version do you have?
<sb0> none, just reading up about it, and it says they need activation after 3 months after which the PC shuts down every hour
<whitequark> hm
<sb0> but for running the unit tests we don't really care
<sb0> we need to checkpoint the VM anyway because the conda garbage rots over time
<sb0> as long as the tests complete in less than hour, the microsoft garbage doesn't get in the way
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<sb0> of course, this stupid maxim smbus dongle requires custom USB drivers and won't work in wine
<sb0> why are electronics companies so much in love with shitty software?
<sb0> hahaha I opened this thing and they have a FTDI chip + a Spartan-3 FPGA inside
<sb0> that's for doing I2C at 400kHz
<sb0> probably they would use zynq with an embedded linux if they were to do it again
<sb0> with Thuderbolt PCIe and custom drivers, of course
<whitequark> actually if they used thunderbolt for that i would be interested
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<bb-m-labs> build #1015 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/1015
<bb-m-labs> build #2878 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2878
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<key2_> whitequark: thunderbolt chipset are easy to find
<key2_> and although the datasheet is hard to get, there are 100s of schematics of laptop out there that show you how they are wired to the pcie
<whitequark> well i know how to wire them
<whitequark> that's not the problem
<whitequark> the problem is that thunderbolt is shit that breaks constantly and without docs you can't fix it
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<keesj> are there examples of combining riscv with migen?
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<key2_> keesj: vexriscv ?
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<marble[m]> Hello
<keesj> hmm Still very confusing all those projects . this one uses nmigen , vexriscv SpinalHDL and the list goes on
<marble[m]> I cannot write to the #solvespace channel :/
<keesj> Hi marble[m]
<marble[m]> can I ask a question here?
<keesj> You can try(I am just a user here)
<keesj> the solverspace forum looks spammed e.g. "Want to start your own business with kaya spirits"
<marble[m]> hmhm
<marble[m]> Is there an easy way to do the platonic solids in solvespace?
<marble[m]> (except for the cube :D )
<marble[m]> there doesn't seem to be an "intersection" operation for extrude and lathe operations
<whitequark> there's an open issue for the intersection operation on the bugtracker
<whitequark> I tried a go at it a few times but was never able to make it work
<marble[m]> oh, okay :/
<keesj> yes this doesn't really fit the "extrude" paradigm
<whitequark> no, it actually should be very simple
<whitequark> it's a permutation of existing operations, a few lines of code
<whitequark> the problem is i suck at math
<marble[m]> ^^
<marble[m]> Is it posible for a solver to be given six connected lines and recognize it as a Tetrahedron?
<marble[m]> becuase free line drawing in 3D space would also be neat
<keesj> well.. that does work
<whitequark> there's another open issue for that
<keesj> there is the sketch in 3d option
<whitequark> no, that doesn't give you surfaces
<whitequark> btw there's a #solvespace channel
<keesj> https://i.imgur.com/6u6e6U2.png no good then?
<marble[m]> my current approach to platonic solids is to extrude a thing, draw the solid in 3D space in the thing, then genereate and new word plane for each face, extrude and substract stuff
<marble[m]> no :/
<marble[m]> For drawing in 3D space, one would need a method to determine which side of the face is "outside" and "inside", right?
<whitequark> you could use the even-odd rule
<keesj> I am getting the following error whe trying to compile misoc for the papilo_pro https://pastebin.com/sumdBxUM
<keesj> https://i.imgur.com/tUxBMUV.png (reset address and rom_size visible)
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<_whitenotifier-c> [nmigen] cr1901 opened pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fhXVp
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/485923234?utm_source=github_status&utm_medium=notification
<_whitenotifier-c> [nmigen] codecov[bot] commented on pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fhXwy
<_whitenotifier-c> [nmigen] whitequark commented on pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fhXwN
<cr1901_modern> https://codecov.io/gh/m-labs/nmigen/pull/33/diff#diff-bm1pZ2VuL2hkbC9pci5weQ== I really don't see where < 50% is coming from
<whitequark> doesn't matter
<cr1901_modern> rebased
<_whitenotifier-c> [nmigen] cr1901 synchronize pull request #33: Give hint when user forgets to return `Module` from `elaborate`. - https://git.io/fhXVp
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/485931508?utm_source=github_status&utm_medium=notification
<keesj> trying to understand my error I am looking at this line https://github.com/m-labs/misoc/blob/master/misoc/integration/soc_core.py#L138
<keesj> the "rom" gets mapped starting a address "cpu_reset_address" but the size of the rom gets substrated from that. that feel odd.
<keesj> (that is on line 140) I would expect rom_size not rom_size-cpu reset address
<keesj> self._memory_regions.append((name, origin, length)) (is the signature of the underlaying code)
<GitHub-m-labs> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/2e8decbce37e...c591009220db
<GitHub-m-labs> artiq/master ed6aa29 Sebastien Bourdeauducq: jesd204sync: print more information on test_slip_ddmtd error
<GitHub-m-labs> artiq/master 9d0d02a Sebastien Bourdeauducq: jesd204sync: increase tolerance for coarse->final target in calibrate_sysref_target...
<GitHub-m-labs> artiq/master c591009 Sebastien Bourdeauducq: sayma: report TSC phase of SYSREF (TSC LSBs on SYSREF rising edge) in SYSREF sampler...
<bb-m-labs> build #2359 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2359
<bb-m-labs> build #2360 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2360
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<keesj> did the status of the papilio prot change much since 2014? e.g. http://forum.gadgetfactory.net/topic/1973-misoc-for-papilio-pro/ SRAM PHY is no supported?
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<jason1_> sb0, acathla, rjo I am trying to use kc705 with the latest version of artiq. I can flash the device and set ip. But I cannot ping the ip that I set. I get destination unreachable. But I can ping the network interface and the router and I also checked all the cables work properly. I also set an ip for my network interface within the range. With the nmap command I cannot see the ip of the kc705. Can you help me to resolve this please? (
<rjo> jason1_: a couple suggestions: make sure the router interface is gigabit. make sure the router interface is up. did you check the leds as requested yesterday? what were the results? do you see arp responses? did you check the uart as suggested yesterday? what were the results there? try connecting the rj45 cable directly to your computer. use a ip address in the same network as your computer.
<rjo> and can you ping other devices in the same (ip and vlan) network as the kc705?
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