sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> sb0: random thought: you know what would be interesting? adding native parameter support to nMigen
<whitequark> that is, in most places where it uses constant integers right now, allow formulas from some computer algebra system
<whitequark> like signal widths
<whitequark> or even easier, allow a subset of Values there.
<whitequark> the *idea* is that this would allow formally verifying a class of modules instead of a single module. the reality is that model checkers can only check single instantiations anyway
<whitequark> this could *also* be interesting in that it could let nMigen emit parameterized Verilog... except then it would not be able to reuse Yosys
<whitequark> because in Yosys parameterized modules are represented with ASTs anyway
<whitequark> so you could as well emit text
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<sb0> whitequark: that's tricky to do properly. if you have a signal with parameterized lenght that you pass into another module, and then that module does various things with len(signal), what happens?
<whitequark> sb0: as long as it never tries to branch on the results of those manipulations, it is fine
<sb0> this is a common use case, and the things that can be done are e.g. signal2 = Signal(len(signal)//4), if len(signal) > threshold, for i in range(len(signal))
<whitequark> the former thing is fine
<whitequark> the latter will not work, which is a price you have to pay
<sb0> then it does not seem very useful
<whitequark> hmm
<whitequark> well, hypothetically, one could map to generate statements
<whitequark> but that seems like it'd involve non-obvious issues
<sb0> yep.
<sb0> and there are many python features that do not map to generate statements
<whitequark> i think it'd still be useful for designs where one has to interoperate back and forth with verilog. not that i have this use case.
<sb0> what would that len() return? and what happens if you attempt to branch on it?
<_whitenotifier-c> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fh45V
<_whitenotifier-c> [m-labs/nmigen] whitequark 66466a8 - back.rtlil: only emit each AnyConst/AnySeq cell once.
<whitequark> sb0: it'd return a Value. probably an Operator
<whitequark> and if you tried to compare and branch it'd be the same "tried to convert nMigen value to bool"
<whitequark> exception that is
<whitequark> (which actually works in nmigen for comparisons as well)
<whitequark> so, you could do something like Signal(len(foo))
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/481160396?utm_source=github_status&utm_medium=notification
<_whitenotifier-c> [nmigen] Failure. 81.73% (-0.13%) compared to 60089db - https://codecov.io/gh/m-labs/nmigen/commit/66466a8a0ec88afc7d5cde272cfe12fd044785ba
<_whitenotifier-c> [nmigen] Failure. 36.36% of diff hit (target 81.85%) - https://codecov.io/gh/m-labs/nmigen/commit/66466a8a0ec88afc7d5cde272cfe12fd044785ba
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/4e142dfbeb94...a467b8f8515d
<GitHub-m-labs> artiq/master a467b8f Sebastien Bourdeauducq: nix: update metadata
<GitHub-m-labs> artiq/master 1e3ef15 Sebastien Bourdeauducq: nix: make versioneer work
<sb0> whitequark: is pythonparser supposed to work on python 3.7?
<whitequark> no, i have a local patch
<bb-m-labs> build #2271 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2271
<bb-m-labs> build #2272 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2272
<bb-m-labs> build #996 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/996
<bb-m-labs> build #2835 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2835
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<GitHub-m-labs> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/8863214277a5d6af9fa7edc1e4aef0e5a325c9bc
<GitHub-m-labs> misoc/master 8863214 Sebastien Bourdeauducq: ku_1000basex: add
<bb-m-labs> build #460 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/460
<GitHub-m-labs> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/52c7549b623f071883c6018abc102da51d9e8748
<GitHub-m-labs> misoc/master 52c7549 Sebastien Bourdeauducq: ku_1000basex: cleanup
<bb-m-labs> build #461 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/461
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<GitHub-m-labs> [artiq] jordens pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/a467b8f8515d...40187d195760
<GitHub-m-labs> artiq/master 2bea5e3 Robert Jördens: urukul: support configurable refclk divider...
<GitHub-m-labs> artiq/master 385916a Robert Jördens: ad9912: support configurable clk_div
<GitHub-m-labs> artiq/master 40187d1 Robert Jördens: ad9910: support configurable refclk divider and pll bypass...
<GitHub-m-labs> [artiq] jordens closed issue #1248: Urukul: direct clocking support without pll and dividers https://github.com/m-labs/artiq/issues/1248
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<GitHub-m-labs> [artiq] jordens commented on issue #1157: Based on a quick check this seems to work at 10 MHz. Someone would need to check how good or bad the loop filter is and what the optimal values are for 10 MHz and pll_n=100. https://github.com/m-labs/artiq/issues/1157#issuecomment-455533326
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<bb-m-labs> build #2273 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2273
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<bb-m-labs> build #2274 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2274
<bb-m-labs> build #997 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/997
<bb-m-labs> build #2836 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2836
<sb0> okay sayma ethernet gth is working with the transceiver in loopback mode
<sb0> (PMA loopback)
<sb0> I'm receving garbage when using the actual SFP, but it's maybe something dumb like an unplugged cable. will check in the lab later.
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