sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
<_whitenotifier-c> [nmigen] whitequark opened issue #29: ResetInserter &c cannot be used on Modules - https://git.io/fh63O
<_whitenotifier-c> [nmigen] whitequark opened issue #30: Module.prepare/rtlil.convert should not propagate inputs to toplevel unless explicitly requested - https://git.io/fh638
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<sb0> hartytp: the hmc7043 fine analog delay seems not to work at all. i don't see any change on ddmtd nor on the dac realigns.
<sb0> I suppose that earlier this issue was masked by the lower clock frequency and the digital delay
<sb0> oh yeah and of course ADI broke all the forum links that contained useful information about the many places where the 7043 datasheet is wrong
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<sb0> ah no, everything works. i had a bug somewhere else.
<sb0> whitequark: do we have rust generators on the core device?
<whitequark> define "rust generator"
<whitequark> #![feature(generator)]
<whitequark> ?
<sb0> yes
<whitequark> even if that feature is technically present, it is guaranteed to be ridden with bugs and compiler crashes
<whitequark> (because the documentation for current rustc master says so)
<whitequark> what do you want generators for?
<sb0> some Sayma SYSREF alignment code that is slightly easier to write using generators
<whitequark> does it do anything complicated like `yield from` in python?
<sb0> no. it's just a FSM with three states.
<whitequark> give it a try, if it's very simple it might work fine.
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<sb0> whitequark: is there something like Vec but which works without allocator (and to which you provide a stack-allocated buffer of the maximum size it could ever have)?
<GitHub-m-labs> [artiq] sbourdeauducq pushed 7 new commits to master: https://github.com/m-labs/artiq/compare/9966e789fcb7...82545605779d
<GitHub-m-labs> artiq/master d1ef036 Sebastien Bourdeauducq: kasli_sawgmaster: initialize SAWG phase according to RTIO TSC
<GitHub-m-labs> artiq/master 8632b55 Sebastien Bourdeauducq: ddmtd: use IOB register to sample input
<GitHub-m-labs> artiq/master f73ffe4 Sebastien Bourdeauducq: firmware: implement DDMTD-based SYSREF/RTIO alignment (draft)...
<bb-m-labs> build #2345 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2345
<sb0> whitequark: also, how do I do a floating point square root?
<bb-m-labs> build #2346 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2346
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<GitHub-m-labs> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/82545605779d...74fdd04622a6
<GitHub-m-labs> artiq/master 81b0046 Sebastien Bourdeauducq: ddmtd: add deglitchers
<GitHub-m-labs> artiq/master 74fdd04 Sebastien Bourdeauducq: firmware: test DDMTD stability
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<sb0> NIST will reopen at 6:00 AM on Monday, January 28, 2019.
<bb-m-labs> build #1011 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/1011
<bb-m-labs> build #2872 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2872
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<bb-m-labs> build #2347 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2347
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<bb-m-labs> build #2348 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2348
<bb-m-labs> build #2873 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2873 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
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<d_n|a> Somewhat off-topic here, but did you see WD's RISC-V core release (32 bit, 2-way superscalar, they claim 4.9 CoreMark/MHz): https://github.com/westerndigitalcorporation/swerv_eh1
<d_n|a> (Looks like it's RV32IMC)
<d_n|a> Probably not very relevant for us (not FPGA-optimised), but good to see movement on that front - even if it's in somewhat painful plain Verilog
<whitequark> sb0: re Vec without allocator: yes. there are a few crates.
<whitequark> sb0: try this one: https://crates.io/crates/fixedvec
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<GitHub37> [smoltcp] crawford opened pull request #272: Allow more integer types when creating Instants (master...instant) https://github.com/m-labs/smoltcp/pull/272
<GitHub168> [smoltcp] whitequark commented on issue #272: You've demonstrated the downside of this PR (thanks!) but what are the concrete upsides? https://github.com/m-labs/smoltcp/pull/272#issuecomment-457959583
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<whitequark> sb0: re: floating point square root
<whitequark> 1.0f.sqrt()
<GitHub93> [smoltcp] crawford commented on issue #272: Instead of writing:... https://github.com/m-labs/smoltcp/pull/272#issuecomment-457960707
<GitHub45> [smoltcp] whitequark commented on issue #272: OK. It seems unlikely that there is a lot of code creating Instants from literals, and the fix is anyhow trivial. https://github.com/m-labs/smoltcp/pull/272#issuecomment-457960959
<GitHub22> [smoltcp] whitequark commented on issue #272: @m-labs-homu r+ https://github.com/m-labs/smoltcp/pull/272#issuecomment-457960964
<GitHub119> [smoltcp] m-labs-homu commented on issue #272: :pushpin: Commit bd63e4e has been approved by `whitequark`
<GitHub129> [smoltcp] m-labs-homu commented on issue #272: :hourglass: Testing commit bd63e4ea18e19020e2fbec0a60460ecc7e2b5a3f with merge d381dcd75fc6a75cb350071a4206629b764474af... https://github.com/m-labs/smoltcp/pull/272#issuecomment-457960992
<GitHub54> [smoltcp] m-labs-homu pushed 1 new commit to auto: https://github.com/m-labs/smoltcp/commit/d381dcd75fc6a75cb350071a4206629b764474af
<GitHub54> smoltcp/auto d381dcd Alex Crawford: Allow more integer types when creating Instants...
<GitHub172> [smoltcp] m-labs-homu commented on issue #272: :sunny: Test successful - [status-travis](https://travis-ci.org/m-labs/smoltcp/builds/485163165?utm_source=github_status&utm_medium=notification)
<travis-ci> m-labs/smoltcp#1194 (auto - d381dcd : Alex Crawford): The build passed.
<GitHub167> [smoltcp] m-labs-homu merged auto into master: https://github.com/m-labs/smoltcp/compare/ed8dce015c45...d381dcd75fc6
<GitHub182> [smoltcp] m-labs-homu closed pull request #272: Allow more integer types when creating Instants (master...instant) https://github.com/m-labs/smoltcp/pull/272
<travis-ci> m-labs/smoltcp#1195 (master - d381dcd : Alex Crawford): The build passed.
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<_whitenotifier-c> [nmigen] whitequark opened issue #31: Record.connect is missing - https://git.io/fh6hw
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