<_whitenotifier-c>
[nmigen] whitequark opened issue #29: ResetInserter &c cannot be used on Modules - https://git.io/fh63O
<_whitenotifier-c>
[nmigen] whitequark opened issue #30: Module.prepare/rtlil.convert should not propagate inputs to toplevel unless explicitly requested - https://git.io/fh638
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<sb0>
hartytp: the hmc7043 fine analog delay seems not to work at all. i don't see any change on ddmtd nor on the dac realigns.
<sb0>
I suppose that earlier this issue was masked by the lower clock frequency and the digital delay
<sb0>
oh yeah and of course ADI broke all the forum links that contained useful information about the many places where the 7043 datasheet is wrong
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<sb0>
ah no, everything works. i had a bug somewhere else.
<sb0>
whitequark: do we have rust generators on the core device?
<whitequark>
define "rust generator"
<whitequark>
#![feature(generator)]
<whitequark>
?
<sb0>
yes
<whitequark>
even if that feature is technically present, it is guaranteed to be ridden with bugs and compiler crashes
<whitequark>
(because the documentation for current rustc master says so)
<whitequark>
what do you want generators for?
<sb0>
some Sayma SYSREF alignment code that is slightly easier to write using generators
<whitequark>
does it do anything complicated like `yield from` in python?
<sb0>
no. it's just a FSM with three states.
<whitequark>
give it a try, if it's very simple it might work fine.
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<sb0>
whitequark: is there something like Vec but which works without allocator (and to which you provide a stack-allocated buffer of the maximum size it could ever have)?
<d_n|a>
Probably not very relevant for us (not FPGA-optimised), but good to see movement on that front - even if it's in somewhat painful plain Verilog
<whitequark>
sb0: re Vec without allocator: yes. there are a few crates.