04:24 <bb-m-labs> build #2807 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2807 blamelist: Drew <drewrisinger@users.noreply.github.com>

05:07 <bb-m-labs> build #2808 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2808 blamelist: Drew <drewrisinger@users.noreply.github.com>

05:17 <bb-m-labs> build #2809 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2809 blamelist: Drew <drewrisinger@users.noreply.github.com>

06:31 <sb0> d_n|a: some race condition on the aux channel

06:32 <sb0> master submit requests A, master times out, satellite answer requests A (which stays in the master buffer), master submits request B, master reads reply A from the buffer and prints an error, satellite answer request B which stays in the master buffer, and so on

06:32 <sb0> this is not supposed to happen, but there is a bug in the code somewhere (most likely master)

10:36 <bb-m-labs> build #2225 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2225

10:51 <bb-m-labs> build #2226 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2226

10:55 <bb-m-labs> build #2810 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2810 blamelist: Robert J?rdens <rj@quartiq.de>

13:24 <Hartytp> rjo: I was asking a while ago about PLL init sequences. FWIW, the ADF5356 data sheet has more info than the 4356 (despite the fact that the PLLs are near identical).

13:27 <Hartytp> the reg 4 write is (a) because the counter reset bit needs to be toggled on these PLLs and (b) because of the double buffering

13:35 <Hartytp> oops, I was looking at 5355, which is a little different, but still the data sheet fills in some gaps

13:35 <Hartytp> of course, the linux driver does something different to the data sheet...

16:14 <_whitenotifier-e> [nmigen] peteut opened issue #24: Project Structure And Tox - https://git.io/fhZ1E

17:15 <_whitenotifier-e> [nmigen] adamgreig commented on issue #20: Memory with only a read port fails in pysim - https://git.io/fhZDL

17:47 <adamgreig> whitequark: my nmigen top module ends up with ports for all unused ports in all submodules, which nextpnr then maps to random io.. any way to just leave them disconnected?

18:06 <adamgreig> (I mean, other than explicitly assigning them all to 0, which I guess is what I want to happen automatically instead of them being pushed up the hierarchy)

18:44 <bb-m-labs> build #2811 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2811 blamelist: Robert J?rdens <rj@quartiq.de>

18:46 <cr1901_modern> yosys needs a "clean unused top levels" pass (no I didn't check whether this exists or not)

18:46 <adamgreig> yes that would do it

18:46 <adamgreig> in migen this doesn't happen, but i guess that's more a quirk of it all being a single module with directly generated verilog

18:47 <adamgreig> having similar sorts of issues where every module has to explicitly add its outputs with frag.add_ports otherwise they're driven but unused inside that module, and unconnected to the output pins at higher levels, which are then output without being driven

18:47 <adamgreig> but i think that's probably by design maybe

18:48 <adamgreig> eg http://dpaste.com/19W2EPQ doesn't work unless you add that port, but it doesn't generate a warning until you try to synthesise

18:50 <adamgreig> but with that in place and with my fix/bodge for #20, i have ported my rmii mac to nmigen and it works on hardware, yay

18:56 <adamgreig> in other words my complaints where inputs getting turned into ports when i didn't want them to be, and outputs not getting turned into ports when i did want them to be :P can't win

18:56 <adamgreig> were*

20:44 <_whitenotifier-e> [nmigen] adamgreig commented on issue #20: Memory with only a read port fails in pysim - https://git.io/fhZHc