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whitequark >
sb0: the migen bits_sign calculation for * is broken
00:43
<
whitequark >
it goes like this:
00:43
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whitequark >
# one operand signed, the other unsigned (add sign bit)
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<
whitequark >
return a_bits + b_bits + 1 - 1, True
00:43
<
whitequark >
but, if you are multiplying C(4,(3,True)) by C(1,(1,False)) you need an extra bit
00:44
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whitequark >
amusingly, you check that case in test_signed, but i think there's a matching bug in simulator.
00:45
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whitequark >
er, wrong case
00:46
<
whitequark >
C(4,(3,True)) by C(-1,(1,True)), is the right case
01:03
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_whitenotifier-c >
[m-labs/nmigen] whitequark f71e0ff - hdl.ast: fix shape calculation for *.
01:03
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 4922a73 - test.compat: import tests from Migen as appropriate.
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_whitenotifier-c >
[m-labs/nmigen] whitequark 4948162 - hdl.ir: rename .get_fragment() to .elaborate().
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key2_ >
whitequark: in this case you need m or m.lower
14:06
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whitequark >
key2_: thanks for reminding, that is another thing i need to fix
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15:15
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sb0 >
of course, with ultrascale, adding the SAWG cranks up the jitter in the DDMTD core quite nicely
15:16
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whitequark >
what affects jitter in an FPGA?
15:18
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sb0 >
it's not using the IOB register, so it's probably picking up noise from the fabric routing
15:18
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sb0 >
recompiling ...
15:19
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sb0 >
good thing I added all sorts of diagnostics to the new sync firmware, so this sort of shenanigan gets flagged immediately
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15:43
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_whitenotifier-c >
[m-labs/nmigen] whitequark 4887771 - compat.sim: fix deprecated stdlib import.
15:43
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 7890c0a - test.compat: reenable tests converting to Verilog.
15:43
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 4bf80a6 - compat: suppress deprecation warnings that are internal or during test.
15:57
<
sb0 >
still jittery with IOB FF... pfff
16:03
<
sb0 >
okay, averaging over several measurements gets rid of it
16:25
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_whitenotifier-c >
[m-labs/nmigen] whitequark b133eb7 - back.rtlil: accept any elaboratable, not just fragments.
16:25
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 7acea8f - examples: update for newer API.
16:36
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sb0 >
rjo: I'm trying to do the equivalent of tracking phase mode on SAWG
16:36
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sb0 >
sawg.frequency0.set_mu(sawg_ftw)
16:36
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sb0 >
sawg.phase0.set_mu(sawg_ftw*now_mu()*4 >> 16)
16:36
<
sb0 >
tried this but does not work
16:38
<
sb0 >
splines 1/2 are at their reset values
16:46
<
sb0 >
aah, got it, now_mu is in 8x rtio
16:46
<
sb0 >
so it's /2 and not *4
16:50
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sb0 >
oooh, it works! I have 2.4GHz Sayma DAC sync'd with Urukul
16:54
<
sb0 >
so, with some hacks, it seems ultrascale can do 2.4GHz timing
18:08
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 8686e9a - back.pysim: give better names to unnamed fragments and their signals.
18:08
<
_whitenotifier-c >
[m-labs/nmigen] whitequark e74dbc3 - back.pysim: support async reset.
18:08
<
_whitenotifier-c >
[m-labs/nmigen] whitequark f44ca29 - lib.cdc: add ResetSynchronizer.
18:24
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 2fb85a6 - compat.fifo: fix _FIFOInterface deprecation wrapper.
18:24
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 6cd9f7d - compat.genlib.resetsync: add shim for AsyncResetSynchronizer.
20:12
<
_whitenotifier-c >
[nmigen] q3k opened issue #27: Simulator: adding two clocks to a single domain causes DeadlineError in simulation -
https://git.io/fh6f6
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23:09
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_whitenotifier-c >
[m-labs/nmigen] whitequark ce7ba70 - compat.fhdl.specials: fix
__all__ list.
23:09
<
_whitenotifier-c >
[m-labs/nmigen] whitequark e844b0e - compat.fhdl.module: fix typo.
23:29
<
_whitenotifier-c >
[m-labs/nmigen] whitequark bc5a127 - hdl.ast: fix ValueKey for Cat.
23:29
<
_whitenotifier-c >
[m-labs/nmigen] whitequark 43e4833 - back.rtlil: accept ast.Const as cell parameter.