sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
<GitHub158> [smoltcp] dlrobertson opened issue #270: Use cfg_if to simplify some cfgs https://github.com/m-labs/smoltcp/issues/270
rohitksingh_work has joined #m-labs
kc5tja has joined #m-labs
rohitksingh_work has quit [Ping timeout: 245 seconds]
rohitksingh_work has joined #m-labs
kc5tja has quit [Quit: Lost terminal]
<GitHub-m-labs> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/81ba8ca4de9a9ba39a8d4586126896e793310cb4
<GitHub-m-labs> migen/master 81ba8ca AlexanderKnapik: Updating Pins of de0nanosoc.py Platform file...
<bb-m-labs> build #364 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/364
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1230: MasterDAC (with 2 or 3 links) is actually not affected, I had made a mistake when testing it the first time. https://github.com/m-labs/artiq/issues/1230#issuecomment-454279706
kc5tja has joined #m-labs
<kc5tja> Anyone have experience working with multiple clock domains using nMigen who can help debug a problem I'm having with a simple circuit?
<kc5tja> Here's the smallest reproducable test case I could come up with: https://gist.github.com/sam-falvo/f7d6a374e01174426205aaa2e0b2611f
<kc5tja> It's almost as if m.domains += xyz *replaces* its collection of domains with xyz, rather than appending/inserting into the collection that's already there.
<kc5tja> (I'll be turning in for the evening shortly; feel free to leave a response here, and I'll check logs tomorrow. Once again, thanks for your time, whoever you may be! :) )
proteusguy has joined #m-labs
kc5tja has left #m-labs [#m-labs]
Rednaxela has joined #m-labs
<Rednaxela> Hmm... so starting to try to synthesize a slightly nontrivial design for the first time with the combination of migen+yosys+nextpnr... and I'm getting a multiple drivers issue for one of the fsm state signals... and in the intermediate verilog I see the problem... but having a hard time seeing anything I might have done in the python code to cause migen to generate multiple drivers on a fsm state...
<Rednaxela> Oh... huh... nevermind... seems the extra driver was way elsewhere in the system... wasn't directly the fsm state that was multiply driven but apparently some multiply driven things did propagate due to yosys rearranging things, causing that to be what errored
m4ssi has joined #m-labs
<_whitenotifier-e> [m-labs/nmigen] sbourdeauducq pushed 1 commit to master [+0/-0/±1] https://git.io/fhcFG
<_whitenotifier-e> [m-labs/nmigen] sbourdeauducq 1880686 - README: add LambdaConcept sponsorship
<_whitenotifier-e> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/479762173?utm_source=github_status&utm_medium=notification
<_whitenotifier-e> [nmigen] Success. 80.4% remains the same compared to c4276f7 - https://codecov.io/gh/m-labs/nmigen/commit/1880686e2e409e3396cd4bdbd5754abb192917b5
<_whitenotifier-e> [nmigen] Success. Coverage not affected when comparing c4276f7...1880686 - https://codecov.io/gh/m-labs/nmigen/commit/1880686e2e409e3396cd4bdbd5754abb192917b5
<GitHub-m-labs> [artiq] AndreCie opened issue #1246: Multiple pipelines https://github.com/m-labs/artiq/issues/1246
<GitHub-m-labs> [artiq] jordens commented on pull request #1244 66b1bfb: Not saying that this is wrong, just trying to understand the rationale: Is the reason that you use 31 here just that it makes both interpreting it as a u32 and upcasting to i64 difficult?... https://github.com/m-labs/artiq/pull/1244#discussion_r247805521
<GitHub-m-labs> [artiq] jordens commented on issue #1246: There can be only one kernel per core device at any time.... https://github.com/m-labs/artiq/issues/1246#issuecomment-454321653
<GitHub-m-labs> [artiq] hartytp opened pull request #1247: issue template: remind users to update the docs (master...master) https://github.com/m-labs/artiq/pull/1247
<adamgreig> kc5tja: you need to add sync yourself if you add any other domains too, it's only added automatically if there are no other (non-comb) domains
<GitHub-m-labs> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/3c0e3e5910b2d75ddbb5b360ad62c36c2ea23c75
<GitHub-m-labs> artiq/master 3c0e3e5 TPH: issue template: remind users to update the docs
<GitHub-m-labs> [artiq] jordens opened issue #1248: Urukul: direct clocking support without pll and dividers https://github.com/m-labs/artiq/issues/1248
<GitHub-m-labs> [artiq] klickverbot pushed 4 new commits to master: https://github.com/m-labs/artiq/compare/3c0e3e5910b2...05f6dafb2cca
<GitHub-m-labs> artiq/master 67a6882 David Nadlinger: examples: Fix kasli_tester device_db offset comments
<GitHub-m-labs> artiq/master a565f77 David Nadlinger: Add gateware input event counter
<GitHub-m-labs> artiq/master 1c71ae6 David Nadlinger: examples: Add edge counters to kasli_tester variant...
<GitHub-m-labs> [artiq] klickverbot closed pull request #1244: Implement gateware-level input edge counters (master...edge-counter) https://github.com/m-labs/artiq/pull/1244
<GitHub-m-labs> [artiq] klickverbot commented on pull request #1244 05f6daf: I'm using 31 bits by default just since using 32 bits is unattractive for user code anyway (have to deal with signedness/extend to i64), and this way we have the extra sign bit to play with in a backwards-compatible fashion in the future (re saturating behaviour vs. wrapping, etc.).... https://github.com/m-labs/artiq/pull/1244#discussion_r2478
<bb-m-labs> build #2258 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2258
Gurty has quit [Read error: Connection timed out]
Gurty has joined #m-labs
<bb-m-labs> build #2259 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2259
<GitHub160> [smoltcp] whitequark commented on issue #270: I vaguely recall some issue with cfg-if as a reason to not use it. But I can't find it now. So I think it's OK. https://github.com/m-labs/smoltcp/issues/270#issuecomment-454359243
<bb-m-labs> build #2828 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2828 blamelist: TPH <thomas.harty@physics.ox.ac.uk>
Gurty has quit [Read error: Connection timed out]
Gurty has joined #m-labs
Gurty has quit [Changing host]
Gurty has joined #m-labs
<bb-m-labs> build #2260 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2260
Gurty has quit [Read error: Connection timed out]
Gurty has joined #m-labs
Gurty has quit [Changing host]
Gurty has joined #m-labs
<bb-m-labs> build #2261 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2261
proteusguy has quit [Quit: Leaving]
<bb-m-labs> build #2829 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2829 blamelist: David Nadlinger <code@klickverbot.at>
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCGe
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCGL
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/689714965b7e28354a7f0d5989c6bac6934e5913
<GitHub-m-labs> artiq/master 6897149 Sebastien Bourdeauducq: monkey_patches: disable for Python >= 3.6.7...
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-4: https://github.com/m-labs/artiq/commit/ea391600069c6c477eff85313e417fe5d2fa0b41
<GitHub-m-labs> artiq/release-4 ea39160 Sebastien Bourdeauducq: monkey_patches: disable for Python >= 3.6.7...
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/87f296c0b57d8d0c3139cc9a9ae1b8df486184d8
<GitHub-m-labs> artiq/release-3 87f296c Sebastien Bourdeauducq: monkey_patches: disable for Python >= 3.6.7...
rohitksingh_work has quit [Read error: Connection reset by peer]
<bb-m-labs> build #2262 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2262
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCC3
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCC2
<bb-m-labs> build #2263 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2263
<bb-m-labs> build #2830 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2830 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1162: @whitequark What is holding this? https://github.com/m-labs/artiq/issues/1162#issuecomment-454390443
<GitHub-m-labs> [artiq] whitequark commented on issue #1162: @sbourdeauducq I wasn't sure how to implement this best, but I just came up with a solution to that. https://github.com/m-labs/artiq/issues/1162#issuecomment-454391800
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCWa
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhClU
rohitksingh has joined #m-labs
<bb-m-labs> build #2264 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2264
<bb-m-labs> build #2265 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2265
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC44
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC4H
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC4Q
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC4b
<bb-m-labs> build #992 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/992
<bb-m-labs> build #2831 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2831
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCBo
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCRI
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCR1
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCR7
proteusguy has joined #m-labs
<_whitenotifier-e> [nmigen] adamgreig commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC0u
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC0K
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhC0M
<bb-m-labs> build #2266 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2266
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCEN
<bb-m-labs> build #993 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/993
<bb-m-labs> build #2832 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2832
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCu8
<_whitenotifier-e> [nmigen] whitequark commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCuK
<_whitenotifier-e> [nmigen] adamgreig commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCuy
m4ssi has quit [Quit: Leaving]
<_whitenotifier-e> [nmigen] jordens commented on issue #9: Bikeshed: design for .get_fragment() - https://git.io/fhCzF
<whitequark> rjo: sb0: can any of you explain to me the semantics of fwft in migen in detail?
<whitequark> annoyingly, it's not documented, and I am having trouble documenting it
<whitequark> it seems to me that non-FWFT mode of SyncFIFO does not match FIFOInterface documentation, or perhaps FIFOInterface is underspecified
whitequark has quit [Quit: Reconnecting]
whitequark has joined #m-labs
<whitequark> sb0: rjo: specifically, it looks to me like SyncFIFO's non-FWFT mode will signal readable without valid data on dout
rohitksingh has joined #m-labs
<sb0> whitequark: yes it will, that's how a non-first-word-fall-through FIFO works
<whitequark> that directly contradicts the docs in FIFOInterface then.
<whitequark> readable : out
<whitequark> Output data `dout` valid, FIFO not empty.
kc5tja has joined #m-labs
<kc5tja> adamgreig: Thank you! I wasn't aware of that requirement. I'll be sure to include that in the updated docs.
mumptai has joined #m-labs
<whitequark> yeah, the more I look at this, the more I think FWFT is a property of the FIFO *interface*, not implementation
<adamgreig> whitequark: I found I had to add a bunch of ports manually to prevent weird things being inferred, but it's probably because i'm using nmigen wrong, and specifically might be because I'm passing pads as signals from the top-level object as parameters into my classes which use them in modules, rather than using comb statements at every layer to connect things
<adamgreig> so each layer needs to say that this pad is an output, and then it works (tm)
<kc5tja> I'm having a new challenge at the moment. I have two modules which use clock domain pix, and a top-level module which intends to drive pix_clk. What is the proper way to do this?
<adamgreig> but I guess the solution is to not pass any signals as parameters to classes, and only have classes make their own signals which i connect to with comb statements
<kc5tja> I've tried the obvious approach where I create a ClockDomain() object for pix, but then attempt to drive it with pix.clk.eq(my_synthesized_clock_here).
<kc5tja> However, this doesn't seem to work. Verilog still exposes all submodule clocks for pix in the interface for top, and doesn't connect the locally generated clock to the submodules.
<kc5tja> I'm guessing now that it's wrong to declare the pix ClockDomain() in the top module, and just rely on combinatorial statements to bind my synthesized clock to submodule clock inputs explicitly?
kc5tja has left #m-labs ["Driving to the day-job office."]
<whitequark> adamgreig: no, that seems like an nmigen bug.
<adamgreig> hm ok, i'll see if i can make a small reproducer
<whitequark> why does line 16 exist?
<adamgreig> sorry yes refresh
<adamgreig> was just mucking with something and didn't delete it
<whitequark> it's still there
<adamgreig> ugh. there we go
<whitequark> sure. you should pass `ports=...` to rtlil.convert
<whitequark> with the complete list of inputs and outputs
<whitequark> this will become required soon
<adamgreig> and that's different to calling frag.add_ports(...) on L35 (the frag from top.get_fragment())?
<adamgreig> it would be nice if the platform or something inside top could do that, since that's what knows about what inputs and outputs it has
<adamgreig> ok, I guess I was mixing up fragment.add_ports and ports= on convert, will see if that resolves all my issues
<adamgreig> at the least I can have my platform return a list of all the ports it gave out
<whitequark> yes, that's the idea
<whitequark> the platform will do that
<adamgreig> will the platform also be responsible for calling rtlil.convert()?
<adamgreig> right now my platform knows all the ports you request()d and returns a pcf file and list of ports to my main(), which just calls frag.add_ports instead of putting it in the rtlil call
<adamgreig> ok, this makes a lot more sense to me now, thanks
<whitequark> platform would call rtlil.convert too, yes
<whitequark> the entire build process
Gurty has joined #m-labs
Gurty has quit [Changing host]
Gurty has joined #m-labs
X-Scale has joined #m-labs
<adamgreig> whitequark: thanks, rejigged to put ports in the convert call and nowhere else and it all works fine
<adamgreig> much better
<adamgreig> and moved building into my platform instead of a makefile so that's nice too
_whitenotifier-c has joined #m-labs
<_whitenotifier-c> [nmigen] cr1901 opened pull request #25: Support for yosys' $anyconst and $anyseq cells - https://git.io/fhWLD
<_whitenotifier-c> [nmigen] whitequark reviewed pull request #25 commit - https://git.io/fhWtI
<_whitenotifier-c> [nmigen] whitequark reviewed pull request #25 commit - https://git.io/fhWtL
<_whitenotifier-c> [nmigen] cr1901 synchronize pull request #25: Support for yosys' $anyconst and $anyseq cells - https://git.io/fhWLD
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/480110241?utm_source=github_status&utm_medium=notification
<_whitenotifier-c> [nmigen] codecov[bot] commented on pull request #25: Support for yosys' $anyconst and $anyseq cells - https://git.io/fhWqE
mumptai has quit [Quit: Verlassend]
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/480114595?utm_source=github_status&utm_medium=notification
<GitHub-m-labs> [artiq] drewrisinger opened issue #1249: Compiler: Generating binary ints https://github.com/m-labs/artiq/issues/1249
<_whitenotifier-c> [nmigen] whitequark closed pull request #25: Support for yosys' $anyconst and $anyseq cells - https://git.io/fhWLD
<_whitenotifier-c> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±5] https://git.io/fhWOB
<_whitenotifier-c> [m-labs/nmigen] cr1901 6fdbc3d - hdl.ast: Add AnyConst and AnySeq value types.
<_whitenotifier-c> [m-labs/nmigen] cr1901 77728c2 - hdl.xfrm: Add on_AnyConst and on_AnySeq abstract methods for ValueVisitor and children.
<_whitenotifier-c> [m-labs/nmigen] cr1901 655d02d - back.rtlil: Generate $anyconst and $anyseq cells.
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/480128491?utm_source=github_status&utm_medium=notification
<_whitenotifier-c> [nmigen] Failure. 80.08% (-0.33%) compared to 1880686 - https://codecov.io/gh/m-labs/nmigen/commit/655d02d5b839d25a349f5e9200ad1d588e80320c
<_whitenotifier-c> [nmigen] Success. Coverage not affected when comparing 1880686...655d02d - https://codecov.io/gh/m-labs/nmigen/commit/655d02d5b839d25a349f5e9200ad1d588e80320c
<_whitenotifier-c> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhW3o
<_whitenotifier-c> [m-labs/nmigen] whitequark 6191760 - Unbreak 655d02d5.
<_whitenotifier-c> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/480134635?utm_source=github_status&utm_medium=notification
<_whitenotifier-c> [nmigen] Success. 80.08% remains the same compared to 655d02d - https://codecov.io/gh/m-labs/nmigen/commit/6191760c308864ede07704a546b19979b1efaf54
<_whitenotifier-c> [nmigen] Success. Coverage not affected when comparing 655d02d...6191760 - https://codecov.io/gh/m-labs/nmigen/commit/6191760c308864ede07704a546b19979b1efaf54
rohitksingh has quit [Ping timeout: 268 seconds]
dlrobertson has joined #m-labs
Gurty has quit [Read error: Connection timed out]
Gurty has joined #m-labs
Gurty has quit [Changing host]
Gurty has joined #m-labs