sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469283303?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxoj
<_whitenotifier-6> [m-labs/nmigen] whitequark d636e36 - Travis: cache Yosys installation explicitly.
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<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469286295?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.51% remains the same compared to c7f9386 - https://codecov.io/gh/m-labs/nmigen/commit/d636e36affdaca9019f265d2572306c29c6b530c
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing c7f9386...d636e36 - https://codecov.io/gh/m-labs/nmigen/commit/d636e36affdaca9019f265d2572306c29c6b530c
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<mithro> whitequark: I kind of like where you are going with nmigen...
<mithro> whitequark: I still dislike the "with xxx" syntax, but I don't like the current syntax either and can't figure out a better solution
<whitequark> yeah
<whitequark> it's just that python is bad for this
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469286295?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] mithro opened issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpx6S
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpx69
<_whitenotifier-6> [m-labs/nmigen] whitequark a743289 - Travis: cache Yosys installation explicitly.
<_whitenotifier-6> [nmigen] whitequark commented on issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpx67
<mithro> whitequark: Why do you use `m.d.sync` and `m.d.comb`?
<whitequark> mithro: clarify your question
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469296145?utm_source=github_status&utm_medium=notification
<mithro> whitequark: Why is there a `.d` in there (rather than assigning to the top level module)?
<whitequark> because we flattened the list of domains
<whitequark> instead of self.comb += you have m.d.comb +=
<mithro> d == clock domain?
<whitequark> instead of self.sync += (which is equivalent to self.sync.sys +=), you have m.d.sync +=
<whitequark> which adds to the domain called "sync"
<whitequark> instead of self.sync.foo +=, you have m.d.foo +=
<whitequark> not clock. just control domain
<whitequark> for now it is only clock domains though.
<whitequark> and comb.
<mithro> could you have two different combinational domains? If so what would you use them for?
<whitequark> no.
<whitequark> not at this point, anyway.
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxiL
<_whitenotifier-6> [m-labs/nmigen] whitequark 51a92bc - Travis: cache Yosys installation explicitly.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469297233?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.51% remains the same compared to c7f9386 - https://codecov.io/gh/m-labs/nmigen/commit/51a92bc8706ab020f519f3867a0fb0e7440fb309
<_whitenotifier-6> [nmigen] Success. Coverage not affected when comparing c7f9386...51a92bc - https://codecov.io/gh/m-labs/nmigen/commit/51a92bc8706ab020f519f3867a0fb0e7440fb309
<mithro> whitequark: So, do you have any thoughts on if we can do something to show equivalence between code in the old format and code in the new format? Would make doing mechanical transform to the new syntax easier....
<whitequark> mithro: what do you mean show equivalence?
<whitequark> mean by*
<mithro> whitequark: That is a good question :-P -- ideally that transforming into the new style hasn't introduced new bugs
<_whitenotifier-6> [nmigen] whitequark commented on issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpxir
<whitequark> mithro: don't you have a testsuite?
<mithro> whitequark: For some things yes
<whitequark> also, what do you mean by mechanical transform?
<whitequark> I think I can make a pythonparser based converter that automatically fixes syntax for well-formed migen code
<_whitenotifier-6> [nmigen] whitequark commented on issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpxiN
<mithro> whitequark: Something like "2to3" for migen -> nmigen type thing...
<whitequark> yes
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<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxyV
<_whitenotifier-6> [m-labs/nmigen] whitequark d6e98fd - back.pysim: continue running simulator processes until they suspend.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469331001?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 77.48% (-0.03%) compared to 51a92bc - https://codecov.io/gh/m-labs/nmigen/commit/d6e98fd934086312c6c08106ec339d37eb99b174
<_whitenotifier-6> [nmigen] Failure. 66.66% of diff hit (target 77.51%) - https://codecov.io/gh/m-labs/nmigen/commit/d6e98fd934086312c6c08106ec339d37eb99b174
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<whitequark> sb0: rjo: is there any good reason migen.sim runs processes *after* doing clk.eq(1) but *before* propagating comb signals?
<whitequark> I guess it sort of makes sense
<whitequark> runs generators*
<whitequark> as if generators were edge triggered
<whitequark> and ran immediately after the clock edge
<attie> isn't that so that if you do (yield sig) after the yield, you get the value without the modifications?
<whitequark> attie: sure but you could always get it on the previous cycle
<whitequark> or... maybe not in migen.sim
<whitequark> you definitely can in nmigen
<whitequark> since any comb changes happen immediately
<whitequark> actually, nevermind what I said
<whitequark> pretty sure migen.sim does the right thing.
<attie> oh, what are you doing for nmigen sim, can you interact with the combinatorial logic now?
<whitequark> define interact
<whitequark> trying to set a signal if that signal is a comb target somewhere in the design is a hard error now, for example
<attie> make a generator that simulates a combinatorial circuit?
<whitequark> no more silently ignored yield x.eq(1)
<whitequark> oh, yeah
<whitequark> i think that could be easily added
<whitequark> like a few lines
<whitequark> if you have a good example, file an issue and i'll actually implement it
<attie> hmm
<attie> all my examples could technically be achieved synchronously too by adding a register stage, I think
<attie> they'd just be easier to do combinatorially
<attie> like, if I have a mux of records, and want to determine where to route the current record
<whitequark> i mean
<whitequark> i don't care if it's only a slight improvement
<whitequark> i just need something to put into tests
<attie> and I want to test different strategies by making the router a generator
<whitequark> and i hate inventing artificial examples
<attie> would that be a good example?
<whitequark> anything that can be put into a few lines of test code works
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxHV
<_whitenotifier-6> [m-labs/nmigen] whitequark 34b81d0 - back.pysim: trigger processes waiting on Tick() exactly at clock edge.
<attie> right, let me see if I can come up with a small thing
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469352560?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 77.45% (-0.04%) compared to d6e98fd - https://codecov.io/gh/m-labs/nmigen/commit/34b81d0b872083020745a7c201476f93d6473158
<_whitenotifier-6> [nmigen] Failure. 0% of diff hit (target 77.48%) - https://codecov.io/gh/m-labs/nmigen/commit/34b81d0b872083020745a7c201476f93d6473158
<attie> I guess you don't need the records really, just a straight up mux will work exactly the same
<whitequark> yeah
<attie> so basically just a mux and a generator that decides the select signal based on the input value
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxH1
<_whitenotifier-6> [m-labs/nmigen] whitequark 6570271 - back.pysim: fix an off-by-1 in add_sync_process().
<attie> where the generator is a simulation model for a yet-to-be-implemented submodule
<whitequark> yep
<whitequark> rjo: ok, the simulator is feature-complete now and i htink it should work exactly as migen.sim.
<whitequark> it is still hideously slow for some reason that i'm not sure what it is, yet
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469353935?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 77.41% (-0.04%) compared to 34b81d0 - https://codecov.io/gh/m-labs/nmigen/commit/65702719e821f0578ef2754b141c287ca08f73f5
<_whitenotifier-6> [nmigen] Failure. 0% of diff hit (target 77.45%) - https://codecov.io/gh/m-labs/nmigen/commit/65702719e821f0578ef2754b141c287ca08f73f5
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<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fpx7J
<_whitenotifier-6> [m-labs/nmigen] whitequark 39605ef - back.pysim: naming. NFC.
<_whitenotifier-6> [m-labs/nmigen] whitequark c5f1699 - back.pysim: use arrays instead of dicts for signal values.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469361963?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.5% (+0.08%) compared to 6570271 - https://codecov.io/gh/m-labs/nmigen/commit/c5f169988bd024e63addedc69d7bf59f68d5dc29
<_whitenotifier-6> [nmigen] Success. 97.77% of diff hit (target 77.41%) - https://codecov.io/gh/m-labs/nmigen/commit/c5f169988bd024e63addedc69d7bf59f68d5dc29
<whitequark> ok, i figure i should write a pysim testsuite now that it works properly
<_whitenotifier-6> [nmigen] nakengelhardt opened issue #11: Make it possible for generators to simulate combinatorial logic - https://git.io/fpx7t
* attie squints at own code dubiously
<attie> without the valid signal that doesn't really make much sense any more, does it.
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<xobs> hi, I'm trying to figure out why a CPU isn't working on litex. I'd like to expose an address line to a GPIO. What I'd like to do is add a Verilog statement like `assign pmod_n3 <= soc_bus_wishbone_adr[2];` How can I do that in Migen?
<attie> self.comb += pmod_n3.eq(soc_bus_wishbone_adr[2])
<attie> the trick is where to put it
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<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±4] https://git.io/fppy4
<whitequark> rjo: ok. i made back.pysim exactly two times faster.
<_whitenotifier-6> [m-labs/nmigen] whitequark 7341d0d - hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
<_whitenotifier-6> [m-labs/nmigen] whitequark 71411c0 - back.pysim: eliminate most dictionary lookups.
<whitequark> (on glasgow testsuite)
<whitequark> unfortunately it is still about 60% slower than migen.sim.
<whitequark> i think it might be because migen.sim fakes clocks and nmigen.back.pysim actually treats them as ordinary comb signals
<whitequark> it's probably possible to recover some of this with more finely grained sensitivity lists...
<_whitenotifier-6> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/469589889?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fpp9T
<_whitenotifier-6> [m-labs/nmigen] whitequark b974583 - back.pysim: eliminate most dictionary lookups.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469594762?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 77.66% (+0.15%) compared to c5f1699 - https://codecov.io/gh/m-labs/nmigen/commit/b9745831e3a7ebe54e65e41b079a728c8f98ddc7
<_whitenotifier-6> [nmigen] Success. 82.11% of diff hit (target 77.5%) - https://codecov.io/gh/m-labs/nmigen/commit/b9745831e3a7ebe54e65e41b079a728c8f98ddc7
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fppHB
<_whitenotifier-6> [m-labs/nmigen] whitequark eb09a78 - back.pysim: eliminate most dictionary lookups.
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fppHu
<_whitenotifier-6> [m-labs/nmigen] whitequark 7fa82a7 - back.pysim: eliminate most dictionary lookups.
<_whitenotifier-6> [nmigen] Error. The Travis CI build could not complete due to an error - https://travis-ci.org/m-labs/nmigen/builds/469599987?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469600053?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. Absolute coverage decreased by -0.08% but relative coverage increased by +1.06% compared to c5f1699 - https://codecov.io/gh/m-labs/nmigen/commit/7fa82a70beae582bf79c6f824830ec283d7d4833
<_whitenotifier-6> [nmigen] Success. 78.57% of diff hit (target 77.5%) - https://codecov.io/gh/m-labs/nmigen/commit/7fa82a70beae582bf79c6f824830ec283d7d4833
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<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±3] https://git.io/fppAn
<_whitenotifier-6> [m-labs/nmigen] whitequark 07e9cfa - test.sim: add tests for sync functionality and errors.
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<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469632985?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Success. 83.01% (+5.58%) compared to 7fa82a7 - https://codecov.io/gh/m-labs/nmigen/commit/07e9cfa9399ba179ac906920d247de4defc17c59
<_whitenotifier-6> [nmigen] Success. 100% of diff hit (target 77.42%) - https://codecov.io/gh/m-labs/nmigen/commit/07e9cfa9399ba179ac906920d247de4defc17c59
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<GitHub-m-labs> [artiq] drewrisinger opened pull request #1220: Misspelling in TDR example (master...dr-pr-examples-tdr-1) https://github.com/m-labs/artiq/pull/1220
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1220: Thanks https://github.com/m-labs/artiq/pull/1220#issuecomment-448327236
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/d60b95f481bb2a9e424ee9e1813bcd36ca7f47d8
<GitHub-m-labs> artiq/master d60b95f Drew: tdr.py: typo (#1220)
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-4: https://github.com/m-labs/artiq/commit/8eee5dd41499fc115fbc7f50b7c2fd9b025b9a9d
<GitHub-m-labs> artiq/release-4 8eee5dd Drew: tdr.py: typo (#1220)
<GitHub-m-labs> [artiq] sbourdeauducq pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/f301ad814d47dd4f12502aaed96614b7557752ae
<GitHub-m-labs> artiq/release-3 f301ad8 Drew: tdr.py: typo (#1220)
<bb-m-labs> build #2153 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2153
<bb-m-labs> build #2154 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2154
<bb-m-labs> build #2769 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2769 blamelist: Drew <drewrisinger@users.noreply.github.com>
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±9] https://git.io/fphIZ
<_whitenotifier-6> [m-labs/nmigen] whitequark 4199674 - back.pysim: implement *.
<_whitenotifier-6> [m-labs/nmigen] whitequark dbbcc49 - hdl.ast: Cat.{operands→parts}
<_whitenotifier-6> [m-labs/nmigen] whitequark a907483 - compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
<_whitenotifier-6> [m-labs/nmigen] whitequark pushed 1 commit to master [+1/-0/±3] https://git.io/fphIg
<_whitenotifier-6> [m-labs/nmigen] whitequark 0f2c7e7 - compat: import genlib.record from Migen.
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469688973?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 78.67% (-4.28%) compared to a907483 - https://codecov.io/gh/m-labs/nmigen/commit/0f2c7e7161328a6dc5b9e808e84dd15dee6228ca
<_whitenotifier-6> [nmigen] Failure. 14.18% of diff hit (target 82.94%) - https://codecov.io/gh/m-labs/nmigen/commit/0f2c7e7161328a6dc5b9e808e84dd15dee6228ca
<_whitenotifier-6> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/469688113?utm_source=github_status&utm_medium=notification
<_whitenotifier-6> [nmigen] Failure. 82.94% (-0.07%) compared to 07e9cfa - https://codecov.io/gh/m-labs/nmigen/commit/a90748303c731ebbf1f8910369e202ddf2e6909e
<_whitenotifier-6> [nmigen] Failure. 76.19% of diff hit (target 83.01%) - https://codecov.io/gh/m-labs/nmigen/commit/a90748303c731ebbf1f8910369e202ddf2e6909e
<bb-m-labs> build #2155 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2155
<bb-m-labs> build #2156 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2156
<bb-m-labs> build #2770 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2770 blamelist: Drew <drewrisinger@users.noreply.github.com>
<bb-m-labs> build #2157 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2157 blamelist: Drew <drewrisinger@users.noreply.github.com>
<bb-m-labs> build #2771 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2771 blamelist: Drew <drewrisinger@users.noreply.github.com>
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