<mithro>
whitequark: So, do you have any thoughts on if we can do something to show equivalence between code in the old format and code in the new format? Would make doing mechanical transform to the new syntax easier....
<whitequark>
mithro: what do you mean show equivalence?
<whitequark>
mean by*
<mithro>
whitequark: That is a good question :-P -- ideally that transforming into the new style hasn't introduced new bugs
<_whitenotifier-6>
[nmigen] whitequark commented on issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpxir
<whitequark>
mithro: don't you have a testsuite?
<mithro>
whitequark: For some things yes
<whitequark>
also, what do you mean by mechanical transform?
<whitequark>
I think I can make a pythonparser based converter that automatically fixes syntax for well-formed migen code
<_whitenotifier-6>
[nmigen] whitequark commented on issue #10: Is there any reason to keep `xxx.submodules`? - https://git.io/fpxiN
<mithro>
whitequark: Something like "2to3" for migen -> nmigen type thing...
<whitequark>
yes
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<_whitenotifier-6>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpxyV
<_whitenotifier-6>
[m-labs/nmigen] whitequark d6e98fd - back.pysim: continue running simulator processes until they suspend.
<whitequark>
ok, i figure i should write a pysim testsuite now that it works properly
<_whitenotifier-6>
[nmigen] nakengelhardt opened issue #11: Make it possible for generators to simulate combinatorial logic - https://git.io/fpx7t
* attie
squints at own code dubiously
<attie>
without the valid signal that doesn't really make much sense any more, does it.
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<xobs>
hi, I'm trying to figure out why a CPU isn't working on litex. I'd like to expose an address line to a GPIO. What I'd like to do is add a Verilog statement like `assign pmod_n3 <= soc_bus_wishbone_adr[2];` How can I do that in Migen?
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<GitHub-m-labs>
[artiq] drewrisinger opened pull request #1220: Misspelling in TDR example (master...dr-pr-examples-tdr-1) https://github.com/m-labs/artiq/pull/1220
<bb-m-labs>
build #2769 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2769 blamelist: Drew <drewrisinger@users.noreply.github.com>
<_whitenotifier-6>
[m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±9] https://git.io/fphIZ
<bb-m-labs>
build #2770 of artiq is complete: Failure [failed python_unittest_3] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2770 blamelist: Drew <drewrisinger@users.noreply.github.com>