<sb0>
a typical bug is forgetting to add this in migen. would there be a way of addressing this issue in nmigen?
<sb0>
iirc yes it's ns
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<whitequark>
sb0: yes. i will have the signals track the modules they are driven from. and if some but not all of these modules are in the final design, nmigen will get angry at you.
<whitequark>
driven/used
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<sb0>
whitequark: for multi clock domain designs, I'd also like signals driven in one domain and sampled in another to cause a warning
<sb0>
unless each such path is explicitly marked by the user as valid
<whitequark>
sure
<whitequark>
that's even easier
<whitequark>
what about I/O pins?
<whitequark>
forgetting a MultiReg is a fairly frequent error
<sb0>
ideally, there should be some framework to automatically instantiate LVDS buffers and such
<sb0>
ah, for CDC
<whitequark>
oh, I have this kind of thing in Glasgow
<whitequark>
maybe we should rethink I/O for nmigen
<sb0>
in artiq there are certain things that are sometimes run over CMOS (on KC705) and LVDS (on Kasli over the ribbon cables)
<sb0>
right now this is not handled in an elegant manner
<sb0>
I guess I/O pins could be marked as asynchronous by default, and also could have a clock domain associated with them
<sb0>
then the same rule applies
<whitequark>
ok
<sb0>
the "asychronous mode" is basically another "invisible" clock domain
<whitequark>
what if one half of a comb signal is driven from domain A and another half from domain B?
<whitequark>
how should this be handled?
<sb0>
1. emit a warning (unless the user says it is valid) 2. treat the result as asynchronous ?
<_whitenotifier>
[nmigen] whitequark opened issue #3: Ensure that all submodules are added to the design - https://git.io/fpbth
<whitequark>
ok
<_whitenotifier>
[nmigen] whitequark opened issue #4: Require signals crossing clock domains to be explicitly marked - https://git.io/fpbqv
<sb0>
also, there should also be warnings for paths that are marked as valid CDC but end up being in the same domain
<_whitenotifier>
[nmigen] whitequark edited issue #4: Require signals crossing clock domains to be explicitly marked - https://git.io/fpbqv
<sb0>
i.e. anything other than marking exactly the CDC paths as valid CDCs results in warnings
<_whitenotifier>
[nmigen] whitequark opened issue #5: Detect multiple drivers in different hierarchical modules - https://git.io/fpbqt
<_whitenotifier>
[nmigen] whitequark edited issue #4: Require signals crossing clock domains to be explicitly marked - https://git.io/fpbqv
<_whitenotifier>
[m-labs/nmigen] whitequark pushed 2 commits to master [+0/-0/±2] https://git.io/fpbqG
<_whitenotifier>
[m-labs/nmigen] whitequark 4f5b4a9 - back.pysim: in simulator sync processes, start by waiting for a tick.
<_whitenotifier>
[m-labs/nmigen] whitequark 120d817 - back.pysim: undriven sync signals should return to previous value.
<sb0>
whitequark: what about supporting CEInserter and such as context managers? (just a random idea...)
<whitequark>
sb0: hmm i'll think about it
<whitequark>
well, CEInserter is just an If.
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<rjo>
whitequark: pong. i registered on that notifico thing. thanks.
<rjo>
whitequark: i haven't had time to test sim and gtkw and pretty much anything on nmigen. but i want to do that soon. ;) but the recent changes look great.
<whitequark>
rjo: there's still a few last bugs in pysim. fishing one now.
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<whitequark>
right, so because of the way FSMs are implemented in compat mode, multiple driver detection and design flattening in nmigen is *mandatory*
<whitequark>
sb0: /home/whitequark/Projects/Glasgow/software/glasgow/gateware/uart.py:231: DriverConflict: Signal '(sig tx_timer)' is driven from multiple fragments: top.dut, top.dut.tx_fsm; hierarchy will be flattened
<d_n|a>
bb-m-labs: force build --branch=pull/1209/merge artiq
<bb-m-labs>
build forced [ETA 1h03m40s]
<bb-m-labs>
I'll give a shout when the build finishes
<_whitenotifier>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fpboj
<_whitenotifier>
[m-labs/nmigen] whitequark 7108111 - back.pysim: preserve process locations through add_sync_process().