<sb0>
any experience using the Andor IXon Ultra 897 with Grabber? does it work?
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<lkcl>
whitequark, sb0: if elif elif chains are taking copies of complex test conditions and duplicating them
<lkcl>
if i can describe how i think if elif elif chains get turned into casez, can you confirm?
<lkcl>
i believe they are done by creating intermediary assignments to temporary variables, representing each individual test of the if and elif conditions
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<lkcl>
and the casez statements are then chained together, so that the 1st casez is simply the 1st if test
<lkcl>
however the 2nd casez is created from the INVERSION of the 1st if test ANDed with the 2nd if test
<lkcl>
and the 3rd casez is created from the inversion of the 1st *AND* 2nd if test, ANDed with the 3rd if test
<lkcl>
and so on
<lkcl>
*however*....
<lkcl>
this is done not by using the intermediate assignments
<lkcl>
it's done by **COPYING** the **ENTIRE** if (or elif) expression
<lkcl>
the way to "avoid" this is by manually assigning the if/elif tests to a temporary intermediate signal with *zero* boolean logic in it
<whitequark>
you're not describing what happens accurately (see e.g. `python3 examples/alu.py generate` for a representative example) and in any case it's not necessary to "avoid" this
<lkcl>
with m.Else():
<lkcl>
whitequark: simple comparisons result in non-duplication
<lkcl>
complex comparisons result in duplication.
<lkcl>
with m.If(self.sel == 0b00):
<lkcl>
will not result in duplication
<lkcl>
with m.If(self.in_a.s == self.in_b.s):
<lkcl>
with m.Elif(self.in_a.m >= self.in_b.m):
<lkcl>
will result in duplication
<lkcl>
why is not necessary to "avoid" duplication?
<whitequark>
why would it be necessary?
<lkcl>
i don't have confidence that the duplicated expressions would be optimised out
<whitequark>
i do
<lkcl>
plus it makes the tools work harder than necessary
<lkcl>
and it makes it much harder to understand the yosys "show" output
<lkcl>
which i am using as a critical tool to ensure the correctness of the auto-generated code
<whitequark>
you should not rely on the yosys graphviz output as a critical tool to ensure correctness; if you do, something is seriously broken with your workflow
<whitequark>
but besides that
<whitequark>
there's no duplication in RTLIL emitted by nmigen; any duplication from if statements that you can see appears inside yosys' write_verilog
<lkcl>
i suspect it would be almost impossible to actually verify the output by visual inspection once it has gone through an optimisation phase
<lkcl>
write_verilog's the culprit? hm, darn.
<lkcl>
that would mean needing to perform temporary assignment of the if/elif to single-signal boolean combinatorial logic prior to handing over to write_verilog
<whitequark>
you don't need it
<whitequark>
a potential fix would be to update write_verilog to take the amount of times a signal is mentioned inside an RTLIL process into account
<whitequark>
but, that'd actually make write_verilog output less readable in many cases, so i'm not very interested in it
<whitequark>
a more appropriate fix would be to reduce rtlil processes to $dff cells, which map to much simpler verilog processes in write_verilog
<whitequark>
and have that as the default verilog output mode
<lkcl>
i don't mind putting things into intermediate signals. i had a couple of cases where there were actual identical expressions duplicated in different if elif elif action blocks
<lkcl>
which i'd missed when writing the code, and only spotted when looking at the graph
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<lkcl>
whitequark, sb0: btw, there's something in the commercial world colloquially known as "spongeing": the act of taking advantage of software libre projects.
<lkcl>
i've applied for a NLnet EU grant. if it comes through (or we receive other funds) i'd like to make sure that you receive some of that money.
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<sb0>
lkcl: thanks! what is your grant/commercial project about?
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<lkcl>
sb0: enhanced privacy and trust, through full transparency, of both software *and* hardware, for an embedded SoC capable of being used in mobile-class devices
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