<_whitenotifier-1>
[nmigen] codecov[bot] commented on pull request #50: Change name seperator for siganls in records to double underscore - https://git.io/fjUft
<_whitenotifier-1>
[nmigen] whitequark closed issue #48: seperator of signal names in records causes ambiguity - https://git.io/fjJ77
<_whitenotifier-1>
[nmigen] whitequark closed pull request #50: Change name seperator for siganls in records to double underscore - https://git.io/fjUv7
<_whitenotifier-1>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjUfE
<_whitenotifier-1>
[m-labs/nmigen] anuejn 3c95299 - hdl.rec: separate record and signal name with __, not _.
<sb0>
whitequark: but migen generates a file that is read by $readmemh for that init attribute
<sb0>
_florent_ changed it to be that way, iirc there was a good reason for that (but I don't remember what it was)
<whitequark>
sb0: I know. that's not really doable if directly emitting RTLIL, maybe with a yosys patch
<whitequark>
though I'm not sure how to write that patch
<whitequark>
$readmemh is interpreted by the Yosys verilog frontend so RTLIL doesn't have any way to represent an operation like that
<_florent_>
sb0: IIRC i needed that when doing a project with Diamond/Lattice, the way we were doing memory initialization was probably not supported by the tools.
<whitequark>
sb0: nevermind, I figured out how to write such a patch
<whitequark>
it would be an addition to Yosys' write_verilog
<whitequark>
a fairly straightforward one
<whitequark>
so if we need that eventually I know how to add it.
<daveshah>
Yeah, I know at least one of the Lattice tools tend to dislike (and silently ignore) initials that aren't either readmemh or readmemb...
<daveshah>
Think that was icecube, not sure about Diamond
<sb0>
whitequark: that's yosys master + the #726 patch
msgctl is now known as loonquawl
<whitequark>
sb0: ah, those aren't broken, they aren't inlined
<whitequark>
even with the #726 patch some signal names aren't going to be inlined because inlining is conservatively suppressed around some Verilog edge cases